From 8708aa2e0eb16a0387d72f8b702171e654abf73e Mon Sep 17 00:00:00 2001 From: schlaepfer Date: Thu, 16 Mar 2006 07:47:05 +0000 Subject: [PATCH] - register element attributes added/changed: * name -> mnemonic * altmnemonic * accessmode * accessattr - register dict updated - Register class redesigned git-svn-id: https://svn.code.sf.net/p/libusbjava/code/trunk@114 94ad28fe-ef68-46b1-9651-e7ae4fcf1c4c --- .../targets/general/registerDictionary.dtd | 9 +- .../targets/mc68332/registerDictionary.dtd | 9 +- .../targets/mc68332/registerDictionary.xml | 277 ++- .../targets/mpc555/registerDictionary.dtd | 9 +- .../targets/mpc555/registerDictionary.xml | 2045 ++++++++++++++--- mcdp/src/ch/ntb/mcdp/dict/Register.java | 147 +- mcdp/src/ch/ntb/mcdp/dict/RegisterDict.java | 21 +- .../ch/ntb/mcdp/mc68332/MC68332Register.java | 6 +- .../ch/ntb/mcdp/mpc555/MPC555Register.java | 6 + 9 files changed, 2052 insertions(+), 477 deletions(-) diff --git a/mcdp/resources/targets/general/registerDictionary.dtd b/mcdp/resources/targets/general/registerDictionary.dtd index 14bdf08..f6bccc3 100644 --- a/mcdp/resources/targets/general/registerDictionary.dtd +++ b/mcdp/resources/targets/general/registerDictionary.dtd @@ -5,14 +5,17 @@ to the specific register used in this registerDict. --> - + + size (1|2|4) #REQUIRED + accessmode (supervisor|user|test) #IMPLIED + accessattr (readonly|writeonly) #IMPLIED> diff --git a/mcdp/resources/targets/mc68332/registerDictionary.dtd b/mcdp/resources/targets/mc68332/registerDictionary.dtd index 11db2f9..b617f4c 100644 --- a/mcdp/resources/targets/mc68332/registerDictionary.dtd +++ b/mcdp/resources/targets/mc68332/registerDictionary.dtd @@ -4,14 +4,17 @@ Only the type values are MC68332 specific. --> - + + size (1|2|4) #REQUIRED + accessmode (supervisor|user|test) #IMPLIED + accessattr (readonly|writeonly) #IMPLIED> diff --git a/mcdp/resources/targets/mc68332/registerDictionary.xml b/mcdp/resources/targets/mc68332/registerDictionary.xml index 6ed2218..417ea3f 100644 --- a/mcdp/resources/targets/mc68332/registerDictionary.xml +++ b/mcdp/resources/targets/mc68332/registerDictionary.xml @@ -5,221 +5,221 @@ - + data register 0 - + data register 1 - + data register 2 - + data register 3 - + data register 43 - + data register 5 - + data register 6 - + data register 7 - + address register 0 - + address register 1 - + address register 2 - + address register 3 - + address register 4 - + address register 5 - + address register 06 - + address register 7 - + return program counter - + current instruction program counter - + status register - + user stack pointer (A7) - + supervisor stack pointer - + source function code register - + destination function code register - + temporary register A - + fault address register - + vector base register - + - sim module configuration register - clock synthesizer control - system protection control - chip select pin assignment register 0 - chip select pin assignment register 1 - CSBOOT base address register - CSBOOT option register - chip select 0 base address register - chip select 0 option register - chip select 1 base address register - chip select 1 option register - chip select 2 base address register - chip select 2 option register - chip select 3 base address register - chip select 3 option register - chip select 4 base address register - chip select 4 option register - chip select 5 base address register - chip select 5 option register - chip select 6 base address register - chip select 6 option register - chip select 7 base address register - chip select 7 option register - chip select 8 base address register - chip select 8 option register - chip select 9 base address register - chip select 9 option register @@ -227,258 +227,297 @@ - TPURAM module configuration register - TPURAM base address and status register - TPU module control register - TPU configuration register - + development support control register - + development support status register - TPU interrupt configuration register - TPU interrupt enable register - channel function select register 0 - channel function select register 1 - channel function select register 2 - channel function select register 3 - + host sequence register 0 - + host sequence register 1 - host service request register 0 - host service request register 1 - + channel priority register 0 - + channel priority register 1 - TPU interrupt status register - + ??? - + service grant latch register - + decoded channel number register - Port E data register 0 - Port E data register 1 - + Port E data direction register - Port E pin assignment register - Port F data register 0 - Port F data register 1 - + Port F data direction register - Port F pin assignment register - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + QSM configuration register - QSM test register - + QSM interrupt level register - + QSM interrupt vector register - SCI control register 0 - SCI control register 1 - + SCI status register - + SCI data register - + QSM port data register - + QSM pin assignment register - + QSM data direction register - QSPI control register 0 - QSPI control register 1 - QSPI control register 2 - QSPI control register 3 - + QSPI status register - + QSPI receive data - + QSPI transmit data - + QSPI command control diff --git a/mcdp/resources/targets/mpc555/registerDictionary.dtd b/mcdp/resources/targets/mpc555/registerDictionary.dtd index 5bd93eb..c86bb4e 100644 --- a/mcdp/resources/targets/mpc555/registerDictionary.dtd +++ b/mcdp/resources/targets/mpc555/registerDictionary.dtd @@ -4,14 +4,17 @@ Only the type values are MPC555 specific. --> - + + size (1|2|4) #REQUIRED + accessmode (supervisor|user|test) #IMPLIED + accessattr (readonly|writeonly) #IMPLIED> diff --git a/mcdp/resources/targets/mpc555/registerDictionary.xml b/mcdp/resources/targets/mpc555/registerDictionary.xml index b579422..ea3867e 100644 --- a/mcdp/resources/targets/mpc555/registerDictionary.xml +++ b/mcdp/resources/targets/mpc555/registerDictionary.xml @@ -5,537 +5,1950 @@ - + General Purpose Register 0 - + General Purpose Register 1 - + General Purpose Register 2 - + General Purpose Register 3 - + General Purpose Register 4 - + General Purpose Register 5 - + General Purpose Register 6 - + General Purpose Register 7 - + General Purpose Register 8 - + General Purpose Register 9 - + General Purpose Register 10 - + General Purpose Register 11 - + General Purpose Register 12 - + General Purpose Register 13 - + General Purpose Register 14 - + General Purpose Register 15 - + General Purpose Register 16 - + General Purpose Register 17 - + General Purpose Register 18 - + General Purpose Register 19 - + General Purpose Register 20 - + General Purpose Register 21 - + General Purpose Register 22 - + General Purpose Register 23 - + General Purpose Register 24 - + General Purpose Register 25 - + General Purpose Register 26 - + General Purpose Register 27 - + General Purpose Register 28 - + General Purpose Register 29 - + General Purpose Register 30 - + General Purpose Register 31 - + Floating-Point Register 0 - + Floating-Point Register 1 - + Floating-Point Register 2 - + Floating-Point Register 3 - + Floating-Point Register 4 - + Floating-Point Register 5 - + Floating-Point Register 6 - + Floating-Point Register 7 - + Floating-Point Register 8 - + Floating-Point Register 9 - + Floating-Point Register 10 - + Floating-Point Register 11 - + Floating-Point Register 12 - + Floating-Point Register 13 - + Floating-Point Register 14 - + Floating-Point Register 15 - + Floating-Point Register 16 - + Floating-Point Register 17 - + Floating-Point Register 18 - + Floating-Point Register 19 - + Floating-Point Register 20 - + Floating-Point Register 21 - + Floating-Point Register 22 - + Floating-Point Register 23 - + Floating-Point Register 24 - + Floating-Point Register 25 - + Floating-Point Register 26 - + Floating-Point Register 27 - + Floating-Point Register 28 - + Floating-Point Register 29 - + Floating-Point Register 30 - + Floating-Point Register 31 - - + + Integer Exception Register (XER) - - Integer Exception Register - - + Link Register (LR) - - Link Register - - + Count Register (CTR) - - Count Register - - - - + DAE/ Source Instruction Service Register (DSISR) - - - DAE/ Source Instruction Service Register - - - + Data Address Register (DAR) - - Data Address Register - - + Decrement Register (DEC) - - Decrement Register - - + Save and Restore Register 0 (SRR0) - - Save and Restore Register 0 + + Save and Restore Register 1 (SRR1) - - Save and Restore Register 1 (SRR0) - - - Save and Restore Register 1 - - + External Interrupt Enable (EIE) - - External Interrupt Enable - - + External Interrupt Disable (EID) - - External Interrupt Disable - - + Non-Recoverable Interrupt (NRI) - - Non-Recoverable Interrupt - - - SPR General 0 (SPRG0) - - - SPR General 0 - - - SPR General 1 (SPRG1) - - - SPR General 1 - - - SPR General 2 (SPRG2) - - - SPR General 2 - - - SPR General 3 (SPRG3) - - - SPR General 3 - - - Time Base Lower - Write (TBL) - - - Time Base Lower - Write - - - Time Base Upper - Write (TBU) - - - Time Base Upper - Write - - - Processor Version Register (PVR) - - - Processor Version Register - - - - I-Cache Control and Status Register (ICCST) - - - - I-Cache Control and Status Register - - - I-Cache Address Register (ICADR) - - - I-Cache Address Register - - - I-Cache Data Port (ICDAT) - - - I-Cache Data Port - - - - Floating-Point Exception Cause Register (FPECR) - - - - - Floating-Point Exception Cause Register - - - - - + Comparator A Value Register (CMPA) - - Comparator A Value Register - - + Comparator B Value Register (CMPB) - - Comparator B Value Register - - + Comparator C Value Register (CMPC) - - Comparator C Value Register - - + Comparator D Value Register (CMPD) - - Comparator D Value Register - - + Exception Cause Register (ECR) - - Exception Cause Register - - + Debug Enable Register (DER) - - Debug Enable Register - - + Breakpoint Counter A Value and Control (COUNTA) - - - Breakpoint Counter A Value and Control - - - + Breakpoint Counter B Value and Control (COUNTB) - - - Breakpoint Counter B Value and Control - - - + Comparator E Value Register (CMPE) - - Comparator E Value Register - - + Comparator F Value Register (CMPF) - - Comparator F Value Register - - + Comparator G Value Register (CMPG) - - Comparator G Value Register - - + Comparator H Value Register (CMPH) - - Comparator H Value Register - - + L-Bus Support Comparators Control (LCTRL1) - - L-Bus Support Comparators Control - - + L-Bus Support Comparators Control (LCTRL2) - - L-Bus Support Comparators Control - - + - I-Bus Suupport Control Register (ICTRL) + I-Bus Support Control Register (ICTRL) - - I-Bus Suupport Control Register - - + Breakpoint Address Register (BAR) - - Breakpoint Address Register + + Time Base Lower - Read (TBLR) - + + Time Base Upper - Read (TBUR) + + + SPR General 0 (SPRG0) + + + SPR General 1 (SPRG1) + + + SPR General 2 (SPRG2) + + + SPR General 3 (SPRG3) + + + Time Base Lower - Write (TBLW) + + + Time Base Upper - Write (TBUW) + + + Processor Version Register (PVR) + + + + Global Region Attribute Register (MI_GRA) + + + + + L2U Global Region Attribute Register (L2U_GRA) + + + + + BBC Module Configuration Register (BBCMCR) + + + + + L2U Module Configuration Register (L2U_MCR) + + + Development Port Data Register (DPDR) - - Development Port Data Register + + Internal Memory Map Register (IMMR) - - - - Time Base Lower - Read (TBL) + + Region Address Register 0 (MI_RBA0) - - Time Base Lower - Read + + Region Address Register 1 (MI_RBA1) - - Time Base Upper - Read (TBU) + + Region Address Register 2 (MI_RBA2) - - Time Base Upper - Read + + Region Address Register 3 (MI_RBA3) - - Time Base Lower - Write + + + L2U Region 0 Address Register (L2U_RBA0) + - - Time Base Upper - Write + + + L2U Region 1 Address Register (L2U_RBA1) + - - + + + L2U Region 2 Address Register (L2U_RBA2) + - - + + + L2U Region 3Address Register (L2U_RBA3) + + + + Region Attribute Register 0 (MI_RA0) + + + Region Attribute Register 1 (MI_RA1) + + + Region Attribute Register 2 (MI_RA2) + + + Region Attribute Register 3 (MI_RA3) + + + + L2U Region 0 Attribute Register (L2U_RA0) + + + + + L2U Region 1 Attribute Register (L2U_RA1) + + + + + L2U Region 2 Attribute Register (L2U_RA2) + + + + + L2U Region 3 Attribute Register (L2U_RA3) + + + + + Floating-Point Exception Cause Register (FPECR) + - + Machine State Register - + Count Register - + Floating-Point Status and Control Register - - Memory Control Base Register 0 - - - Memory Control Option Register 0 - - - Memory Control Base Register 1 - - - Memory Control Option Register 1 - - - Memory Control Base Register 2 - - - Memory Control Option Register 2 - - - Memory Control Base Register 3 - - - Memory Control Option Register 3 - - - Dual Mapping Base Register - - - Dual Mapping Option Register - - - Reset Status Register - - - System Protection Control Register - + + + + + + SIU Module Configuration Register + + + + System Protection Control Register + + + + Software Service Register + + + Interrupt Pending Register + + + Interrupt Mask Register + + + Interrupt Edge Level Mask + + + Interrupt Vector + + + Transfer Error Status Register + + + + USIU General-Purpose I/O Data Register 1 + + + + + USIU General-Purpose I/O Data Register 2 + + + + + USIU General-Purpose I/O Control Register + + + + + External Master Mode Control Register + + + + + Pads Module Configuration Register + + + + + + Memory Control Base Register 0 + + + Memory Control Option Register 0 + + + Memory Control Base Register 1 + + + Memory Control Option Register 1 + + + Memory Control Base Register 2 + + + Memory Control Option Register 2 + + + Memory Control Base Register 3 + + + Memory Control Option Register 3 + + + Dual Mapping Base Register + + + Dual Mapping Option Register + + + Memory Status + + + + + Time Base Status and Control + + + Time Base Reference 0 + + + Time Base Reference 1 + + + + Real Time Clock Status and Control + + + + Real Time Clock + + + Real Time Alarm Seconds + + + Real Time Alarm + + + PIT Status and Control + + + PIT Count + + + PIT Register + + + + + System Clock Control Register + + + + PLL Low Power and Reset Control Register + + + + Reset Status Register + + + Change of Lock Interrupt Register + + + VDDSRM Control Register + + + + + Time Base Status and Control Key + + + Time Base Reference 0 Key + + + Time Base Reference 1 Key + + + Time Base and Decrementer Key + + + + Real-Time Clock Status and Control Key + + + + Real-Time Clock Key + + + Real-Time Alarm Seconds Key + + + Real-Time Alarm Key + + + PIT Status and Control Key + + + PIT Count Key + + + + + System Clock Control Key + + + + PLL Low-Power and Reset Control Register Key + + + + Reset Status Register Key + + + + + + + CMF_A EEPROM Configuration Register + + + + CMF_A EEPROM Test Register + + + + CMF_A EEPROM High Voltage Control Register + + + + + + CMF_B EEPROM Configuration Register + + + + CMF_B EEPROM Test Register + + + + CMF_B EEPROM High Voltage Control Register + + + + + + + + DPT Module Configuration Register + + + Test register, factory test only + + + RAM Array Address Register + + + + Multiple Input Signature Register High + + + + + Multiple Input Signature Register Low + + + + MISC Counter + + + + + + + + + TPU3_A Module Configuration Register + + + + + TPU3_A Test Configuration Register + + + + + TPU3_A Development Support Control Register + + + + + TPU3_A Development Support Status Register + + + + + TPU3_A Interrupt Configuration Register. + + + + + TPU3_A Channel Interrupt Enable Register + + + + + TPU3_A Channel Function Selection Register 0. + + + + + TPU3_A Channel Function Selection Register 1 + + + + + TPU3_A Channel Function Selection Register 2 + + + + + TPU_A Channel Function Selection Register 3 + + + + TPU_A Host Sequence Register 0 + + + TPU_A Host Sequence Register 1 + + + + TPU_A Host Service Request Register 0 + + + + + TPU_A Host Service Request Register 1 + + + + TPU_A Channel Priority Register 0 + + + TPU_A Channel Priority Register 1 + + + + TPU_A Channel Interrupt Status Register + + + + TPU_A Link Register + + + + TPU_A Service Grant Latch Register + + + + + TPU_A Decoded Channel Number Register + + + + + TPU_A Module Configuration Register 2 + + + + + TPU_A Module Configuration Register 3 + + + + TPU_A Internal Scan Data Register + + + + TPU_A Internal Scan Control Register + + + + + + TPU3_B Module Configuration Register + + + + + TPU3_B Test Configuration Register + + + + + TPU3_B Development Support Control Register + + + + + TPU3_B Development Support Status Register + + + + + TPU3_B Interrupt Configuration Register + + + + + TPU3_B Channel Interrupt Enable Register + + + + + TPU3_B Channel Function Selection Register 0 + + + + + TPU3_B Channel Function Selection Register 1 + + + + + TPU3_B Channel Function Selection Register 2 + + + + + TPU_B Channel Function Selection Register 3 + + + + TPU_B Host Sequence Register 0 + + + TPU_B Host Sequence Register 1 + + + + TPU_B Host Service Request Register 0 + + + + + TPU_B Host Service Request Register 1 + + + + TPU_B Channel Priority Register 0 + + + TPU_B Channel Priority Register 1 + + + + TPU_B Channel Interrupt Status Register + + + + TPU_B Link Register + + + + TPU_B Service Grant Latch Register + + + + + TPU_B Decoded Channel Number Register + + + + + TPU_B Module Configuration Register 2 + + + + + TPU_B Module Configuration Register 3 + + + + TPU_B Internal Scan Data Register + + + + TPU_B Internal Scan Control Register + + + + + + + + + + QADC64 Module Configuration Register + + + + QADC64 Test Register + + + QADC64 Interrupt Register + + + Port A and Port B Data + + + + Port A Data and Port B Direction Register + + + + QADC64 Control Register 0 + + + QADC64 Control Register 1 + + + QADC64 Control Register 2 + + + QADC64 Status Register 0 + + + QADC64 Status Register 1 + + + + + QADC64 Module Configuration Register + + + + QADC64 Test Register + + + QADC64 Interrupt Register + + + Port A and Port B Data + + + + Port A Data and Port B Direction Register + + + + QADC64 Control Register 0 + + + QADC64 Control Register 1 + + + QADC64 Control Register 2 + + + QADC64 Status Register 0 + + + QADC64 Status Register 1 + + + + + + + + QSMCM Module Configuration Register + + + + QSMCM Test Register + + + Dual SCI Interrupt Level + + + Queued SPI Interrupt Level + + + SCI1Control Register 0 + + + SCI1Control Register 1 + + + SCI1 Status Register + + + SCI1 Data Register + + + QSMCM Port QS Data Register + + + + QSMCM Port QS PIn Assignment Register / QSMCM Port QS + Data Direction Register + + + + QSPI Control Register 0 + + + QSPI Control Register 1 + + + QSPI Control Register 2 + + + QSPI Control Register 3 + + + QSPI Status Register 3 + + + SCI2 Control Register 0 + + + SCI2 Control Register 1 + + + SCI2 Status Register + + + SCI2 Data Register + + + QSCI1 Control Register + + + QSCI1 Status Register + + + + + + + + MPWMSM0 Period Register + + + MPWMSM0 Pulse Register + + + MPWMSM0 Count Register + + + MPWMSM0 Status/Control Register + + + + MPWMSM1 Period Register + + + MPWMSM1 Pulse Register + + + MPWMSM1 Count Register + + + MPWMSM1 Status/Control Register + + + + MPWMSM2 Period Register + + + MPWMSM2 Pulse Register + + + MPWMSM2 Count Register + + + MPWMSM2 Status/Control Register + + + + MPWMSM3 Period Register + + + MPWMSM3 Pulse Register + + + MPWMSM3 Count Register + + + MPWMSM3 Status/Control Register + + + + MMCSM6 Up-Counter Register + + + MMCSM6 Modulus Latch Register + + + + MMCSM6 Status/Control Register Duplicated + + + + MMCSM6 Status/Control Register + + + + MDASM11 Data A Register + + + MDASM11 Data B Register + + + + MDASM11 Status/Control Register Duplicated + + + + MDASM11 Status/Control Register + + + + MDASM12 Data A Register + + + MDASM12 Data B Register + + + + MDASM12 Status/Control Register Duplicated + + + + MDASM12 Status/Control Register + + + + MDASM13 Data A Register + + + MDASM13 Data B Register + + + + MDASM13 Status/Control Register Duplicated + + + + MDASM13 Status/Control Register + + + + MDASM14 Data A Register + + + MDASM14 Data B Register + + + + MDASM14 Status/Control Register Duplicated + + + + MDASM14 Status/Control Register + + + + MDASM15 Data A Register + + + MDASM15 Data B Register + + + + MDASM15 Status/Control Register Duplicated + + + + MDASM15 Status/Control Register + + + + MPWMSM16 Period Register + + + MPWMSM16 Pulse Register + + + MPWMSM16 Count Register + + + MPWMSM16 Status/Control Register + + + + MPWMSM17 Period Register + + + MPWMSM17 Pulse Register + + + MPWMSM17 Count Register + + + MPWMSM17 Status/Control Register + + + + MPWMSM18 Period Register + + + MPWMSM18 Pulse Register + + + MPWMSM18 Count Register + + + MPWMSM18 Status/Control Register + + + + MPWMSM19 Period Register + + + MPWMSM19 Pulse Register + + + MPWMSM19 Count Register + + + MPWMSM19 Status/Control Register + + + + MMCSM22 Up-Counter Register + + + MMCSM22 Modulus Latch Register + + + + MMCSM22 Status/Control Register Duplicated + + + + MMCSM22 Status/Control Register + + + + MDASM27 Data A Register + + + MDASM27 Data B Register + + + + MDASM27 Status/Control Register Duplicated + + + + MDASM27 Status/Control Register + + + + MDASM28 Data A Register + + + MDASM28 Data B Register + + + + MDASM28 Status/Control Register Duplicated + + + + MDASM28 Status/Control Register + + + + MDASM29 Data A Register + + + MDASM29 Data B Register + + + + MDASM29 Status/Control Register Duplicated + + + + MDASM29 Status/Control Register + + + + MDASM30 Data A Register + + + MDASM30 Data B Register + + + + MDASM30 Status/Control Register Duplicated + + + + MDASM30 Status/Control Register + + + + MDASM31 Data A Register + + + MDASM31 Data B Register + + + + MDASM31 Status/Control Register Duplicated + + + + MDASM31 Status/Control Register + + + + MPIOSM Data Register + + + MPIOSM Data Direction Register + + + + + MIOS1 Test and Pin Control Register. + + + + + MIOS1 Module Version Number Register + + + + MIOS1 Module Control Register + + + + MCPSM Status/Control Register + + + + MIRSM0 Interrupt Status Register + + + MIRSM0 Interrupt Enable Register + + + MIRSM0 Request Pending Register + + + + MIOS1 Interrupt Level Register 0 + + + + MIRSM1 Interrupt Status Register + + + MIRSM1 Interrupt Enable Register + + + MIRSM1 Request Pending Register + + + + MIOS1 Interrupt Level Register 1 + + + + + + + + + TouCAN_A Module Configuration Register. + + + + TouCAN_A Test Register + + + + TouCAN_A Interrupt Configuration Register. + + + + + TouCAN_A Control Register 0 / TouCAN_A Control Register + 1 + + + + + TouCAN_A Control and Prescaler Divider Register / + TouCAN_A Control Register 2 + + + + + TouCAN_A Free-Running Timer Register. + + + + TouCAN_A Receive Global Mask High + + + TouCAN_A Receive Global Mask Low + + + + TouCAN_A Receive Buffer 14 Mask High + + + + + TouCAN_A Receive Buffer 14 Mask Low + + + + + TouCAN_A Receive Buffer 15 Mask High + + + + + TouCAN_A Receive Buffer 15 Mask Low + + + + + TouCAN_A Error and Status Register + + + + TouCAN_A Interrupt Masks + + + TouCAN_A Interrupt Flags + + + + TouCAN_A Receive Error Counter / TouCAN_A Transmit Error + Counter + + + + + + TouCAN_B Module Configuration Register. + + + + TouCAN_B Test Register + + + + TouCAN_B Interrupt Configuration Register. + + + + + TouCAN_B Control Register 0 / TouCAN_B Control Register + 1 + + + + + TouCAN_B Control and Prescaler Divider Register / + TouCAN_B Control Register 2 + + + + + TouCAN_B Free-Running Timer Register. + + + + TouCAN_B Receive Global Mask High + + + TouCAN_B Receive Global Mask Low + + + + TouCAN_B Receive Buffer 14 Mask High + + + + + TouCAN_B Receive Buffer 14 Mask Low + + + + + TouCAN_B Receive Buffer 15 Mask High + + + + + TouCAN_B Receive Buffer 15 Mask Low + + + + + TouCAN_B Error and Status Register + + + + TouCAN_B Interrupt Masks + + + TouCAN_B Interrupt Flags + + + + TouCAN_B Receive Error Counter / TouCAN_B Transmit Error + Counter + + + + + + UIMB Module Configuration Register + + + + + Test Register — Reserved + + + Pending Interrupt Request Registe + + + + + + + + + SRAM_A Module Configuration Register + + + + SRAM_A Test Register + + + + + SRAM_B Module Configuration Register + + + + SRAM_B Test Register + + + diff --git a/mcdp/src/ch/ntb/mcdp/dict/Register.java b/mcdp/src/ch/ntb/mcdp/dict/Register.java index 2ee0a8d..a831d83 100644 --- a/mcdp/src/ch/ntb/mcdp/dict/Register.java +++ b/mcdp/src/ch/ntb/mcdp/dict/Register.java @@ -7,6 +7,8 @@ package ch.ntb.mcdp.dict; */ public abstract class Register { + private static final String INIT_STRING = "***"; + /** * Register specific type values.
* The index of each type in the types array represents its numeric value. @@ -19,59 +21,154 @@ public abstract class Register { protected static String[] types = null; /** - * Name of the register. Registers are identified by this value. + * Menemoic of the register. Registers are identified by this value. */ - public String name = "NOT INITIALISED"; + private String mnemonic = INIT_STRING; + + /** + * Alternative mnemonic of the register + */ + private String altmnemonic = INIT_STRING; /** * Register specific type */ - public int type; + private int type; /** * Address or a register specific value (e.g. BDI-identifier) */ - public int value; + private int value; /** * Size in bytes (width) */ - public int size; + private int size; /** * A string description of the register */ - public String description; + private String description; /** - * @param name - * name of the register. Registers are identified by this value. - * @param type - * register specific type - * @param value - * address or a register specific value (e.g. BDI-identifier) - * @param size - * size in bytes - * @param description - * a string description of the register + * @return the mnemonic of this register */ - public void init(String name, int type, int value, int size, - String description) { - this.name = name; - this.type = type; - this.value = value; - this.size = size; + public String getMnemonic() { + return mnemonic; + } + + /** + * Set the mnemonic of this register + * + * @param name + */ + public void setMnemonic(String name) { + this.mnemonic = name; + } + + /** + * @return alternative mnemonic of the register + */ + public String getAltmnemonic() { + return altmnemonic; + } + + /** + * Set the alternative name of the register. + * + * @param altname + */ + public void setAltmnemonic(String altname) { + this.altmnemonic = altname; + } + + /** + * @return the register description + */ + public String getDescription() { + return description; + } + + /** + * Set the register description. + * + * @param description + */ + public void setDescription(String description) { this.description = description; } + /** + * @return the size in bytes (width) + */ + public int getSize() { + return size; + } + + /** + * Set the size in bytes (width) + * + * @param size + */ + public void setSize(int size) { + this.size = size; + } + + /** + * @return the type of the register. This is the index of the static + * types String array. + */ + public int getType() { + return type; + } + + /** + * Set the type of the register. This is the index of the static + * types String array. + * + * @param type + */ + public void setType(int type) { + this.type = type; + } + + /** + * @return the address or a register specific value (e.g. BDI-identifier) + */ + public int getValue() { + return value; + } + + /** + * Set the address or a register specific value (e.g. BDI-identifier). + * + * @param value + */ + public void setValue(int value) { + this.value = value; + } + + /** + * @return true if a mnemonic was set and the size is valid (size > 0), else + * false + */ + public boolean isValid() { + if ((mnemonic == INIT_STRING) || (size <= 0)) + return false; + return true; + } + @Override public String toString() { - return new String(name + "\t" + types[type] + "\t0x" - + Integer.toHexString(value) + "\t" + size + "\t" + description); + return new String(mnemonic + "\t" + altmnemonic + "\t" + types[type] + + "\t0x" + Integer.toHexString(value) + "\t" + size + "\t" + + description); } /** - * Get the register specific type strings. + * Get the register specific type strings. This value has to be initialised + * in the static section of the derived Register class as + * this is Register specific. * * @return types strings */ diff --git a/mcdp/src/ch/ntb/mcdp/dict/RegisterDict.java b/mcdp/src/ch/ntb/mcdp/dict/RegisterDict.java index cb599e5..2b8d650 100644 --- a/mcdp/src/ch/ntb/mcdp/dict/RegisterDict.java +++ b/mcdp/src/ch/ntb/mcdp/dict/RegisterDict.java @@ -52,7 +52,7 @@ public abstract class RegisterDict { private static final String DESCRIPTION = "description"; - private static final String REG_ATTR_NAME = "name"; + private static final String REG_ATTR_MNEMONIC = "mnemonic"; private static final String REG_ATTR_TYPE = "type"; @@ -104,16 +104,22 @@ public abstract class RegisterDict { String description) { // remove before add for updates for (Iterator i = registers.iterator(); i.hasNext();) { - if (((Register) i.next()).name.equals(name)) { + Register r = (Register) i.next(); + if (r.getMnemonic().equals(name) || r.getAltmnemonic().equals(name)) { i.remove(); } } Register reg = null; try { reg = (Register) regClass.newInstance(); - reg.init(name, type, value, size, description); + reg.setMnemonic(name); + reg.setType(type); + reg.setValue(value); + reg.setSize(size); + reg.setDescription(description); } catch (Exception e) { e.printStackTrace(); + // TODO exception handling System.exit(1); } registers.add(reg); @@ -149,7 +155,7 @@ public abstract class RegisterDict { public Register getRegister(String name) { for (Iterator i = registers.iterator(); i.hasNext();) { Register r = (Register) i.next(); - if (r.name.equals(name)) { + if (r.getMnemonic().equals(name) || r.getAltmnemonic().equals(name)) { return r; } } @@ -162,7 +168,8 @@ public abstract class RegisterDict { public void printRegisters() { System.out .println("******************** register dictionary *********************"); - System.out.println("Name\tType\tAddress\tSize\tDescription"); + System.out + .println("Mnemonic\tAltmnemonic\tType\tAddress\tSize\tDescription"); System.out .println("**************************************************************"); for (Iterator i = registers.iterator(); i.hasNext();) { @@ -235,7 +242,7 @@ public abstract class RegisterDict { } else if (list.item(j).getNodeName().equals(REGISTER)) { NamedNodeMap attributes = list.item(j).getAttributes(); // attributes: name, type, offset, size - Node n = attributes.getNamedItem(REG_ATTR_NAME); + Node n = attributes.getNamedItem(REG_ATTR_MNEMONIC); String name = n.getNodeValue(); n = attributes.getNamedItem(REG_ATTR_TYPE); String typeStr = n.getNodeValue(); @@ -266,7 +273,7 @@ public abstract class RegisterDict { if (list.item(i).getNodeName().equals(REGISTER)) { NamedNodeMap attributes = list.item(i).getAttributes(); // attributes: name, type, offset, size - Node n = attributes.getNamedItem(REG_ATTR_NAME); + Node n = attributes.getNamedItem(REG_ATTR_MNEMONIC); String name = n.getNodeValue(); n = attributes.getNamedItem(REG_ATTR_TYPE); String typeStr = n.getNodeValue(); diff --git a/mcdp/src/ch/ntb/mcdp/mc68332/MC68332Register.java b/mcdp/src/ch/ntb/mcdp/mc68332/MC68332Register.java index 036f554..7c57672 100644 --- a/mcdp/src/ch/ntb/mcdp/mc68332/MC68332Register.java +++ b/mcdp/src/ch/ntb/mcdp/mc68332/MC68332Register.java @@ -3,11 +3,15 @@ package ch.ntb.mcdp.mc68332; import ch.ntb.mcdp.dict.Register; /** + * Representation of a MC68332 Register + * * For system and user registers the value value is used as BDI * specific identifier (code specific to each register from the Technical * Reference Manual). + * + * @author schlaepfer + * */ - public class MC68332Register extends Register { // Register Types diff --git a/mcdp/src/ch/ntb/mcdp/mpc555/MPC555Register.java b/mcdp/src/ch/ntb/mcdp/mpc555/MPC555Register.java index 47d650e..0a0072e 100644 --- a/mcdp/src/ch/ntb/mcdp/mpc555/MPC555Register.java +++ b/mcdp/src/ch/ntb/mcdp/mpc555/MPC555Register.java @@ -2,6 +2,12 @@ package ch.ntb.mcdp.mpc555; import ch.ntb.mcdp.dict.Register; +/** + * Representation of a MPC555 Register + * + * @author schlaepfer + * + */ public class MPC555Register extends Register { // Register Types