diff --git a/mcdp/resources/targets/mc68332/registerDictionary.dtd b/mcdp/resources/targets/mc68332/registerDictionary.dtd index b77ba24..11db2f9 100644 --- a/mcdp/resources/targets/mc68332/registerDictionary.dtd +++ b/mcdp/resources/targets/mc68332/registerDictionary.dtd @@ -1,8 +1,10 @@ - + - + @@ -10,6 +12,6 @@ diff --git a/mcdp/resources/targets/mc68332/registerDictionary.xml b/mcdp/resources/targets/mc68332/registerDictionary.xml index 7c3c91b..6ed2218 100644 --- a/mcdp/resources/targets/mc68332/registerDictionary.xml +++ b/mcdp/resources/targets/mc68332/registerDictionary.xml @@ -4,118 +4,222 @@ + + + data register 0 + + + data register 1 + + + data register 2 + + + data register 3 + + + data register 43 + + + data register 5 + + + data register 6 + + + data register 7 + + + + + address register 0 + + + address register 1 + + + address register 2 + + + address register 3 + + + address register 4 + + + address register 5 + + + address register 06 + + + address register 7 + + + + + return program counter + + + current instruction program counter + + + status register + + + user stack pointer (A7) + + + supervisor stack pointer + + + source function code register + + + destination function code register + + + temporary register A + + + fault address register + + + vector base register + + - sim module configuration register - clock synthesizer control - system protection control - chip select pin assignment register 0 - chip select pin assignment register 1 - CSBOOT base address register - CSBOOT option register - - chip select 0 base address register + + chip select 0 base address register + - chip select 0 option register - - chip select 1 base address register + + chip select 1 base address register + - chip select 1 option register - - chip select 2 base address register + + chip select 2 base address register + - chip select 2 option register - - chip select 3 base address register + + chip select 3 base address register + - chip select 3 option register - - chip select 4 base address register + + chip select 4 base address register + - chip select 4 option register - - chip select 5 base address register + + chip select 5 base address register + - chip select 5 option register - - chip select 6 base address register + + chip select 6 base address register + - chip select 6 option register - - chip select 7 base address register + + chip select 7 base address register + - chip select 7 option register - - chip select 8 base address register + + chip select 8 base address register + - chip select 8 option register - - chip select 9 base address register + + chip select 9 base address register + - chip select 9 option register @@ -123,279 +227,258 @@ - - TPURAM module configuration register + + TPURAM module configuration register + - - TPURAM base address and status register + + TPURAM base address and status register + - - TPU module control register - TPU configuration register - - development support control register + + + development support control register + - - development support status register + + + development support status register + - - TPU interrupt configuration register + + TPU interrupt configuration register + - TPU interrupt enable register - - channel function select register 0 + + channel function select register 0 + - - channel function select register 1 + + channel function select register 1 + - - channel function select register 2 + + channel function select register 2 + - - channel function select register 3 + + channel function select register 3 + - + host sequence register 0 - + host sequence register 1 - host service request register 0 - host service request register 1 - + channel priority register 0 - + channel priority register 1 - TPU interrupt status register - + ??? - + service grant latch register - + decoded channel number register - Port E data register 0 - Port E data register 1 - + Port E data direction register - Port E pin assignment register - Port F data register 0 - Port F data register 1 - + Port F data direction register - Port F pin assignment register - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + TPU parameter ram start address - + QSM configuration register - QSM test register - + QSM interrupt level register - + QSM interrupt vector register - SCI control register 0 - SCI control register 1 - + SCI status register - + SCI data register - + QSM port data register - + QSM pin assignment register - + QSM data direction register - QSPI control register 0 - QSPI control register 1 - QSPI control register 2 - QSPI control register 3 - + QSPI status register - + QSPI receive data - + QSPI transmit data - + QSPI command control diff --git a/mcdp/resources/targets/mpc555/registerDictionary.dtd b/mcdp/resources/targets/mpc555/registerDictionary.dtd new file mode 100644 index 0000000..5bd93eb --- /dev/null +++ b/mcdp/resources/targets/mpc555/registerDictionary.dtd @@ -0,0 +1,17 @@ + + + + + + + + + + diff --git a/mcdp/resources/targets/mpc555/registerDictionary.xml b/mcdp/resources/targets/mpc555/registerDictionary.xml new file mode 100644 index 0000000..f99848b --- /dev/null +++ b/mcdp/resources/targets/mpc555/registerDictionary.xml @@ -0,0 +1,370 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +