General Purpose Register 0 General Purpose Register 1 General Purpose Register 2 General Purpose Register 3 General Purpose Register 4 General Purpose Register 5 General Purpose Register 6 General Purpose Register 7 General Purpose Register 8 General Purpose Register 9 General Purpose Register 10 General Purpose Register 11 General Purpose Register 12 General Purpose Register 13 General Purpose Register 14 General Purpose Register 15 General Purpose Register 16 General Purpose Register 17 General Purpose Register 18 General Purpose Register 19 General Purpose Register 20 General Purpose Register 21 General Purpose Register 22 General Purpose Register 23 General Purpose Register 24 General Purpose Register 25 General Purpose Register 26 General Purpose Register 27 General Purpose Register 28 General Purpose Register 29 General Purpose Register 30 General Purpose Register 31 Floating-Point Register 0 Floating-Point Register 1 Floating-Point Register 2 Floating-Point Register 3 Floating-Point Register 4 Floating-Point Register 5 Floating-Point Register 6 Floating-Point Register 7 Floating-Point Register 8 Floating-Point Register 9 Floating-Point Register 10 Floating-Point Register 11 Floating-Point Register 12 Floating-Point Register 13 Floating-Point Register 14 Floating-Point Register 15 Floating-Point Register 16 Floating-Point Register 17 Floating-Point Register 18 Floating-Point Register 19 Floating-Point Register 20 Floating-Point Register 21 Floating-Point Register 22 Floating-Point Register 23 Floating-Point Register 24 Floating-Point Register 25 Floating-Point Register 26 Floating-Point Register 27 Floating-Point Register 28 Floating-Point Register 29 Floating-Point Register 30 Floating-Point Register 31 Integer Exception Register (XER) Link Register (LR) Count Register (CTR) DAE/ Source Instruction Service Register (DSISR) Data Address Register (DAR) Decrement Register (DEC) Save and Restore Register 0 (SRR0) Save and Restore Register 1 (SRR1) External Interrupt Enable (EIE) External Interrupt Disable (EID) Non-Recoverable Interrupt (NRI) Comparator A Value Register (CMPA) Comparator B Value Register (CMPB) Comparator C Value Register (CMPC) Comparator D Value Register (CMPD) Exception Cause Register (ECR) Debug Enable Register (DER) Breakpoint Counter A Value and Control (COUNTA) Breakpoint Counter B Value and Control (COUNTB) Comparator E Value Register (CMPE) Comparator F Value Register (CMPF) Comparator G Value Register (CMPG) Comparator H Value Register (CMPH) L-Bus Support Comparators Control (LCTRL1) L-Bus Support Comparators Control (LCTRL2) I-Bus Support Control Register (ICTRL) Breakpoint Address Register (BAR) Time Base Lower - Read (TBLR) Time Base Upper - Read (TBUR) SPR General 0 (SPRG0) SPR General 1 (SPRG1) SPR General 2 (SPRG2) SPR General 3 (SPRG3) Time Base Lower - Write (TBLW) Time Base Upper - Write (TBUW) Processor Version Register (PVR) Global Region Attribute Register (MI_GRA) L2U Global Region Attribute Register (L2U_GRA) BBC Module Configuration Register (BBCMCR) L2U Module Configuration Register (L2U_MCR) Development Port Data Register (DPDR) Internal Memory Map Register (IMMR) Region Address Register 0 (MI_RBA0) Region Address Register 1 (MI_RBA1) Region Address Register 2 (MI_RBA2) Region Address Register 3 (MI_RBA3) L2U Region 0 Address Register (L2U_RBA0) L2U Region 1 Address Register (L2U_RBA1) L2U Region 2 Address Register (L2U_RBA2) L2U Region 3Address Register (L2U_RBA3) Region Attribute Register 0 (MI_RA0) Region Attribute Register 1 (MI_RA1) Region Attribute Register 2 (MI_RA2) Region Attribute Register 3 (MI_RA3) L2U Region 0 Attribute Register (L2U_RA0) L2U Region 1 Attribute Register (L2U_RA1) L2U Region 2 Attribute Register (L2U_RA2) L2U Region 3 Attribute Register (L2U_RA3) Floating-Point Exception Cause Register (FPECR) Machine State Register Count Register Floating-Point Status and Control Register SIU Module Configuration Register System Protection Control Register Software Service Register Interrupt Pending Register Interrupt Mask Register Interrupt Edge Level Mask Interrupt Vector Transfer Error Status Register USIU General-Purpose I/O Data Register 1 USIU General-Purpose I/O Data Register 2 USIU General-Purpose I/O Control Register External Master Mode Control Register Pads Module Configuration Register Memory Control Base Register 0 Memory Control Option Register 0 Memory Control Base Register 1 Memory Control Option Register 1 Memory Control Base Register 2 Memory Control Option Register 2 Memory Control Base Register 3 Memory Control Option Register 3 Dual Mapping Base Register Dual Mapping Option Register Memory Status Time Base Status and Control Time Base Reference 0 Time Base Reference 1 Real Time Clock Status and Control Real Time Clock Real Time Alarm Seconds Real Time Alarm PIT Status and Control PIT Count PIT Register System Clock Control Register PLL Low Power and Reset Control Register Reset Status Register Change of Lock Interrupt Register VDDSRM Control Register Time Base Status and Control Key Time Base Reference 0 Key Time Base Reference 1 Key Time Base and Decrementer Key Real-Time Clock Status and Control Key Real-Time Clock Key Real-Time Alarm Seconds Key Real-Time Alarm Key PIT Status and Control Key PIT Count Key System Clock Control Key PLL Low-Power and Reset Control Register Key Reset Status Register Key CMF_A EEPROM Configuration Register CMF_A EEPROM Test Register CMF_A EEPROM High Voltage Control Register CMF_B EEPROM Configuration Register CMF_B EEPROM Test Register CMF_B EEPROM High Voltage Control Register DPT Module Configuration Register Test register, factory test only RAM Array Address Register Multiple Input Signature Register High Multiple Input Signature Register Low MISC Counter TPU3_A Module Configuration Register TPU3_A Test Configuration Register TPU3_A Development Support Control Register TPU3_A Development Support Status Register TPU3_A Interrupt Configuration Register. TPU3_A Channel Interrupt Enable Register TPU3_A Channel Function Selection Register 0. TPU3_A Channel Function Selection Register 1 TPU3_A Channel Function Selection Register 2 TPU_A Channel Function Selection Register 3 TPU_A Host Sequence Register 0 TPU_A Host Sequence Register 1 TPU_A Host Service Request Register 0 TPU_A Host Service Request Register 1 TPU_A Channel Priority Register 0 TPU_A Channel Priority Register 1 TPU_A Channel Interrupt Status Register TPU_A Link Register TPU_A Service Grant Latch Register TPU_A Decoded Channel Number Register TPU_A Module Configuration Register 2 TPU_A Module Configuration Register 3 TPU_A Internal Scan Data Register TPU_A Internal Scan Control Register TPU3_B Module Configuration Register TPU3_B Test Configuration Register TPU3_B Development Support Control Register TPU3_B Development Support Status Register TPU3_B Interrupt Configuration Register TPU3_B Channel Interrupt Enable Register TPU3_B Channel Function Selection Register 0 TPU3_B Channel Function Selection Register 1 TPU3_B Channel Function Selection Register 2 TPU_B Channel Function Selection Register 3 TPU_B Host Sequence Register 0 TPU_B Host Sequence Register 1 TPU_B Host Service Request Register 0 TPU_B Host Service Request Register 1 TPU_B Channel Priority Register 0 TPU_B Channel Priority Register 1 TPU_B Channel Interrupt Status Register TPU_B Link Register TPU_B Service Grant Latch Register TPU_B Decoded Channel Number Register TPU_B Module Configuration Register 2 TPU_B Module Configuration Register 3 TPU_B Internal Scan Data Register TPU_B Internal Scan Control Register QADC64 Module Configuration Register QADC64 Test Register QADC64 Interrupt Register Port A and Port B Data Port A Data and Port B Direction Register QADC64 Control Register 0 QADC64 Control Register 1 QADC64 Control Register 2 QADC64 Status Register 0 QADC64 Status Register 1 QADC64 Module Configuration Register QADC64 Test Register QADC64 Interrupt Register Port A and Port B Data Port A Data and Port B Direction Register QADC64 Control Register 0 QADC64 Control Register 1 QADC64 Control Register 2 QADC64 Status Register 0 QADC64 Status Register 1 QSMCM Module Configuration Register QSMCM Test Register Dual SCI Interrupt Level Queued SPI Interrupt Level SCI1Control Register 0 SCI1Control Register 1 SCI1 Status Register SCI1 Data Register QSMCM Port QS Data Register QSMCM Port QS PIn Assignment Register / QSMCM Port QS Data Direction Register QSPI Control Register 0 QSPI Control Register 1 QSPI Control Register 2 QSPI Control Register 3 QSPI Status Register 3 SCI2 Control Register 0 SCI2 Control Register 1 SCI2 Status Register SCI2 Data Register QSCI1 Control Register QSCI1 Status Register MPWMSM0 Period Register MPWMSM0 Pulse Register MPWMSM0 Count Register MPWMSM0 Status/Control Register MPWMSM1 Period Register MPWMSM1 Pulse Register MPWMSM1 Count Register MPWMSM1 Status/Control Register MPWMSM2 Period Register MPWMSM2 Pulse Register MPWMSM2 Count Register MPWMSM2 Status/Control Register MPWMSM3 Period Register MPWMSM3 Pulse Register MPWMSM3 Count Register MPWMSM3 Status/Control Register MMCSM6 Up-Counter Register MMCSM6 Modulus Latch Register MMCSM6 Status/Control Register Duplicated MMCSM6 Status/Control Register MDASM11 Data A Register MDASM11 Data B Register MDASM11 Status/Control Register Duplicated MDASM11 Status/Control Register MDASM12 Data A Register MDASM12 Data B Register MDASM12 Status/Control Register Duplicated MDASM12 Status/Control Register MDASM13 Data A Register MDASM13 Data B Register MDASM13 Status/Control Register Duplicated MDASM13 Status/Control Register MDASM14 Data A Register MDASM14 Data B Register MDASM14 Status/Control Register Duplicated MDASM14 Status/Control Register MDASM15 Data A Register MDASM15 Data B Register MDASM15 Status/Control Register Duplicated MDASM15 Status/Control Register MPWMSM16 Period Register MPWMSM16 Pulse Register MPWMSM16 Count Register MPWMSM16 Status/Control Register MPWMSM17 Period Register MPWMSM17 Pulse Register MPWMSM17 Count Register MPWMSM17 Status/Control Register MPWMSM18 Period Register MPWMSM18 Pulse Register MPWMSM18 Count Register MPWMSM18 Status/Control Register MPWMSM19 Period Register MPWMSM19 Pulse Register MPWMSM19 Count Register MPWMSM19 Status/Control Register MMCSM22 Up-Counter Register MMCSM22 Modulus Latch Register MMCSM22 Status/Control Register Duplicated MMCSM22 Status/Control Register MDASM27 Data A Register MDASM27 Data B Register MDASM27 Status/Control Register Duplicated MDASM27 Status/Control Register MDASM28 Data A Register MDASM28 Data B Register MDASM28 Status/Control Register Duplicated MDASM28 Status/Control Register MDASM29 Data A Register MDASM29 Data B Register MDASM29 Status/Control Register Duplicated MDASM29 Status/Control Register MDASM30 Data A Register MDASM30 Data B Register MDASM30 Status/Control Register Duplicated MDASM30 Status/Control Register MDASM31 Data A Register MDASM31 Data B Register MDASM31 Status/Control Register Duplicated MDASM31 Status/Control Register MPIOSM Data Register MPIOSM Data Direction Register MIOS1 Test and Pin Control Register. MIOS1 Module Version Number Register MIOS1 Module Control Register MCPSM Status/Control Register MIRSM0 Interrupt Status Register MIRSM0 Interrupt Enable Register MIRSM0 Request Pending Register MIOS1 Interrupt Level Register 0 MIRSM1 Interrupt Status Register MIRSM1 Interrupt Enable Register MIRSM1 Request Pending Register MIOS1 Interrupt Level Register 1 TouCAN_A Module Configuration Register. TouCAN_A Test Register TouCAN_A Interrupt Configuration Register. TouCAN_A Control Register 0 / TouCAN_A Control Register 1 TouCAN_A Control and Prescaler Divider Register / TouCAN_A Control Register 2 TouCAN_A Free-Running Timer Register. TouCAN_A Receive Global Mask High TouCAN_A Receive Global Mask Low TouCAN_A Receive Buffer 14 Mask High TouCAN_A Receive Buffer 14 Mask Low TouCAN_A Receive Buffer 15 Mask High TouCAN_A Receive Buffer 15 Mask Low TouCAN_A Error and Status Register TouCAN_A Interrupt Masks TouCAN_A Interrupt Flags TouCAN_A Receive Error Counter / TouCAN_A Transmit Error Counter TouCAN_B Module Configuration Register. TouCAN_B Test Register TouCAN_B Interrupt Configuration Register. TouCAN_B Control Register 0 / TouCAN_B Control Register 1 TouCAN_B Control and Prescaler Divider Register / TouCAN_B Control Register 2 TouCAN_B Free-Running Timer Register. TouCAN_B Receive Global Mask High TouCAN_B Receive Global Mask Low TouCAN_B Receive Buffer 14 Mask High TouCAN_B Receive Buffer 14 Mask Low TouCAN_B Receive Buffer 15 Mask High TouCAN_B Receive Buffer 15 Mask Low TouCAN_B Error and Status Register TouCAN_B Interrupt Masks TouCAN_B Interrupt Flags TouCAN_B Receive Error Counter / TouCAN_B Transmit Error Counter UIMB Module Configuration Register Test Register — Reserved Pending Interrupt Request Registe SRAM_A Module Configuration Register SRAM_A Test Register SRAM_B Module Configuration Register SRAM_B Test Register