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8708aa2e0eb16a0387d72f8b702171e654abf73e
jlibusb/mcdp/resources/targets/mc68332/registerDictionary.xml
schlaepfer 8708aa2e0e - register element attributes added/changed: 
* name -> mnemonic
* altmnemonic
* accessmode
* accessattr
- register dict updated
- Register class redesigned

git-svn-id: https://svn.code.sf.net/p/libusbjava/code/trunk@114 94ad28fe-ef68-46b1-9651-e7ae4fcf1c4c
2006-03-16 07:47:05 +00:00

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18 KiB
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<?xml version='1.0' encoding='utf-8'?>
<!-- Register Definitions for the Motorola MC68332 Microcontroller -->
<!DOCTYPE registerDefinitions SYSTEM "registerDictionary.dtd">
<registerDefinitions>
<!-- data registers -->
<register mnemonic="D0" type="UserReg" value="0x0" size="4">
<description>data register 0</description>
</register>
<register mnemonic="D1" type="UserReg" value="0x1" size="4">
<description>data register 1</description>
</register>
<register mnemonic="D2" type="UserReg" value="0x2" size="4">
<description>data register 2</description>
</register>
<register mnemonic="D3" type="UserReg" value="3" size="4">
<description>data register 3</description>
</register>
<register mnemonic="D4" type="UserReg" value="4" size="4">
<description>data register 43</description>
</register>
<register mnemonic="D5" type="UserReg" value="5" size="4">
<description>data register 5</description>
</register>
<register mnemonic="D6" type="UserReg" value="6" size="4">
<description>data register 6</description>
</register>
<register mnemonic="D7" type="UserReg" value="7" size="4">
<description>data register 7</description>
</register>
<!-- address registers -->
<register mnemonic="A0" type="UserReg" value="0x8" size="4">
<description>address register 0</description>
</register>
<register mnemonic="A1" type="UserReg" value="0x9" size="4">
<description>address register 1</description>
</register>
<register mnemonic="A2" type="UserReg" value="0xA" size="4">
<description>address register 2</description>
</register>
<register mnemonic="A3" type="UserReg" value="0xB" size="4">
<description>address register 3</description>
</register>
<register mnemonic="A4" type="UserReg" value="0xC" size="4">
<description>address register 4</description>
</register>
<register mnemonic="A5" type="UserReg" value="0xD" size="4">
<description>address register 5</description>
</register>
<register mnemonic="A6" type="UserReg" value="0xE" size="4">
<description>address register 06</description>
</register>
<register mnemonic="A7" type="UserReg" value="0xF" size="4">
<description>address register 7</description>
</register>
<!-- system registers -->
<register mnemonic="RPC" type="SysReg" value="0x0" size="4">
<description>return program counter</description>
</register>
<register mnemonic="PCC" type="SysReg" value="0x1" size="4">
<description>current instruction program counter</description>
</register>
<register mnemonic="SR" type="SysReg" value="0xB" size="2">
<description>status register</description>
</register>
<register mnemonic="USP" type="SysReg" value="0xC" size="4">
<description>user stack pointer (A7)</description>
</register>
<register mnemonic="SSP" type="SysReg" value="0xD" size="4">
<description>supervisor stack pointer</description>
</register>
<register mnemonic="SFC" type="SysReg" value="0xE" size="4">
<description>source function code register</description>
</register>
<register mnemonic="DFC" type="SysReg" value="0xF" size="4">
<description>destination function code register</description>
</register>
<register mnemonic="ATEMP" type="SysReg" value="0x8" size="4">
<description>temporary register A</description>
</register>
<register mnemonic="FAR" type="SysReg" value="0x9" size="4">
<description>fault address register</description>
</register>
<register mnemonic="VBR" type="SysReg" value="0xA" size="4">
<description>vector base register</description>
</register>
<registerGroup baseAddress="0xFFFFF000">
<!-- control registers -->
<register mnemonic="SIMCR" type="CtrlReg" value="0x0A00"
size="2">
<description>sim module configuration register</description>
</register>
<register mnemonic="SYNCR" type="CtrlReg" value="0x0A04"
size="2">
<description>clock synthesizer control</description>
</register>
<register mnemonic="SYPCR" type="CtrlReg" value="0x0A20"
size="2">
<description>system protection control</description>
</register>
<register mnemonic="CSPAR0" type="CtrlReg" value="0x0A44"
size="2">
<description>
chip select pin assignment register 0
</description>
</register>
<register mnemonic="CSPAR1" type="CtrlReg" value="0x0A46"
size="2">
<description>
chip select pin assignment register 1
</description>
</register>
<register mnemonic="CSBARBT" type="CtrlReg" value="0x0A48"
size="2">
<description>CSBOOT base address register</description>
</register>
<register mnemonic="CSORBT" type="CtrlReg" value="0x0A4A"
size="2">
<description>CSBOOT option register</description>
</register>
<register mnemonic="CSBAR0" type="CtrlReg" value="0x0A4C"
size="2">
<description>
chip select 0 base address register
</description>
</register>
<register mnemonic="CSOR0" type="CtrlReg" value="0x0A4E"
size="2">
<description>chip select 0 option register</description>
</register>
<register mnemonic="CSBAR1" type="CtrlReg" value="0x0A50"
size="2">
<description>
chip select 1 base address register
</description>
</register>
<register mnemonic="CSOR1" type="CtrlReg" value="0x0A52"
size="2">
<description>chip select 1 option register</description>
</register>
<register mnemonic="CSBAR2" type="CtrlReg" value="0x0A54"
size="2">
<description>
chip select 2 base address register
</description>
</register>
<register mnemonic="CSOR2" type="CtrlReg" value="0x0A56"
size="2">
<description>chip select 2 option register</description>
</register>
<register mnemonic="CSBAR3" type="CtrlReg" value="0x0A58"
size="2">
<description>
chip select 3 base address register
</description>
</register>
<register mnemonic="CSOR3" type="CtrlReg" value="0x0A5A"
size="2">
<description>chip select 3 option register</description>
</register>
<register mnemonic="CSBAR4" type="CtrlReg" value="0x0A5C"
size="2">
<description>
chip select 4 base address register
</description>
</register>
<register mnemonic="CSOR4" type="CtrlReg" value="0x0A5E"
size="2">
<description>chip select 4 option register</description>
</register>
<register mnemonic="CSBAR5" type="CtrlReg" value="0x0A60"
size="2">
<description>
chip select 5 base address register
</description>
</register>
<register mnemonic="CSOR5" type="CtrlReg" value="0x0A62"
size="2">
<description>chip select 5 option register</description>
</register>
<register mnemonic="CSBAR6" type="CtrlReg" value="0x0A64"
size="2">
<description>
chip select 6 base address register
</description>
</register>
<register mnemonic="CSOR6" type="CtrlReg" value="0x0A66"
size="2">
<description>chip select 6 option register</description>
</register>
<register mnemonic="CSBAR7" type="CtrlReg" value="0x0A68"
size="2">
<description>
chip select 7 base address register
</description>
</register>
<register mnemonic="CSOR7" type="CtrlReg" value="0x0A6A"
size="2">
<description>chip select 7 option register</description>
</register>
<register mnemonic="CSBAR8" type="CtrlReg" value="0x0A6C"
size="2">
<description>
chip select 8 base address register
</description>
</register>
<register mnemonic="CSOR8" type="CtrlReg" value="0x0A6E"
size="2">
<description>chip select 8 option register</description>
</register>
<register mnemonic="CSBAR9" type="CtrlReg" value="0x0A70"
size="2">
<description>
chip select 9 base address register
</description>
</register>
<register mnemonic="CSOR9" type="CtrlReg" value="0x0A72"
size="2">
<description>chip select 9 option register</description>
</register>
<!-- TPU registers -->
<!-- adjust the setting of tpumcr to reflect modmap bit -->
<register mnemonic="TRAMMCR" type="CtrlReg" value="0x0B00"
size="2">
<description>
TPURAM module configuration register
</description>
</register>
<register mnemonic="TRAMBAR" type="CtrlReg" value="0x0B04"
size="2">
<description>
TPURAM base address and status register
</description>
</register>
<register mnemonic="TPUMCR" type="CtrlReg" value="0x0E00"
size="2">
<description>TPU module control register</description>
</register>
<register mnemonic="TPUCFG" type="CtrlReg" value="0x0E02"
size="2">
<description>TPU configuration register</description>
</register>
<register mnemonic="DSCR" type="CtrlReg" value="0x0E04"
size="2">
<description>
development support control register
</description>
</register>
<register mnemonic="DSSR" type="CtrlReg" value="0x0E06"
size="2">
<description>
development support status register
</description>
</register>
<register mnemonic="TPUICR" type="CtrlReg" value="0x0E08"
size="2">
<description>
TPU interrupt configuration register
</description>
</register>
<register mnemonic="TPUIER" type="CtrlReg" value="0x0E0A"
size="2">
<description>TPU interrupt enable register</description>
</register>
<register mnemonic="CFSR0" type="CtrlReg" value="0x0E0C"
size="2">
<description>
channel function select register 0
</description>
</register>
<register mnemonic="CFSR1" type="CtrlReg" value="0x0E0E"
size="2">
<description>
channel function select register 1
</description>
</register>
<register mnemonic="CFSR2" type="CtrlReg" value="0x0E10"
size="2">
<description>
channel function select register 2
</description>
</register>
<register mnemonic="CFSR3" type="CtrlReg" value="0x0E12"
size="2">
<description>
channel function select register 3
</description>
</register>
<register mnemonic="HSR0" type="CtrlReg" value="0x0E14"
size="2">
<description>host sequence register 0</description>
</register>
<register mnemonic="HSR1" type="CtrlReg" value="0x0E16"
size="2">
<description>host sequence register 1</description>
</register>
<register mnemonic="HSRR0" type="CtrlReg" value="0x0E18"
size="2">
<description>host service request register 0</description>
</register>
<register mnemonic="HSRR1" type="CtrlReg" value="0x0E1A"
size="2">
<description>host service request register 1</description>
</register>
<register mnemonic="CPR0" type="CtrlReg" value="0x0E1C"
size="2">
<description>channel priority register 0</description>
</register>
<register mnemonic="CPR1" type="CtrlReg" value="0x0E1E"
size="2">
<description>channel priority register 1</description>
</register>
<register mnemonic="TPUISR" type="CtrlReg" value="0x0E20"
size="2">
<description>TPU interrupt status register</description>
</register>
<register mnemonic="LINK" type="CtrlReg" value="0x0E22"
size="2">
<description>???</description>
</register>
<register mnemonic="SGLR" type="CtrlReg" value="0x0E24"
size="2">
<description>service grant latch register</description>
</register>
<register mnemonic="DCNR" type="CtrlReg" value="0x0E26"
size="2">
<description>decoded channel number register</description>
</register>
<!-- Port E Registers -->
<register mnemonic="PORTE0" type="CtrlReg" value="0x0A11"
size="1">
<description>Port E data register 0</description>
</register>
<register mnemonic="PORTE1" type="CtrlReg" value="0x0A13"
size="1">
<description>Port E data register 1</description>
</register>
<register mnemonic="DDRE" type="CtrlReg" value="0x0A15"
size="1">
<description>Port E data direction register</description>
</register>
<register mnemonic="PEPAR" type="CtrlReg" value="0x0A17"
size="1">
<description>Port E pin assignment register</description>
</register>
<!-- Port F Registers -->
<register mnemonic="PORTF0" type="CtrlReg" value="0x0A19"
size="1">
<description>Port F data register 0</description>
</register>
<register mnemonic="PORTF1" type="CtrlReg" value="0x0A1B"
size="1">
<description>Port F data register 1</description>
</register>
<register mnemonic="DDRF" type="CtrlReg" value="0x0A1D"
size="1">
<description>Port F data direction register</description>
</register>
<register mnemonic="PFPAR" type="CtrlReg" value="0x0A1F"
size="1">
<description>Port F pin assignment register</description>
</register>
<!-- TPU parameter ram start addresses -->
<register mnemonic="CH0" type="CtrlReg" value="0x0F00"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH1" type="CtrlReg" value="0x0F10"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH2" type="CtrlReg" value="0x0F20"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH3" type="CtrlReg" value="0x0F30"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH4" type="CtrlReg" value="0x0F40"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH5" type="CtrlReg" value="0x0F50"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH6" type="CtrlReg" value="0x0F60"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH7" type="CtrlReg" value="0x0F70"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH8" type="CtrlReg" value="0x0F80"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH9" type="CtrlReg" value="0x0F90"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH10" type="CtrlReg" value="0x0FA0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH11" type="CtrlReg" value="0x0FB0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH12" type="CtrlReg" value="0x0FC0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH13" type="CtrlReg" value="0x0FD0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH14" type="CtrlReg" value="0x0FE0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register mnemonic="CH15" type="CtrlReg" value="0x0FF0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<!-- queued serial module -->
<register mnemonic="QMCR" type="CtrlReg" value="0x0C00"
size="2">
<description>QSM configuration register</description>
</register>
<register mnemonic="QTEST" type="CtrlReg" value="0x0C02"
size="2">
<description>QSM test register</description>
</register>
<register mnemonic="QILR" type="CtrlReg" value="0x0C04"
size="1">
<description>QSM interrupt level register</description>
</register>
<register mnemonic="QIVR" type="CtrlReg" value="0x0C05"
size="1">
<description>QSM interrupt vector register</description>
</register>
<register mnemonic="SCCR0" type="CtrlReg" value="0x0C08"
size="2">
<description>SCI control register 0</description>
</register>
<register mnemonic="SCCR1" type="CtrlReg" value="0x0C0A"
size="2">
<description>SCI control register 1</description>
</register>
<register mnemonic="SCSR" type="CtrlReg" value="0x0C0C"
size="2">
<description>SCI status register</description>
</register>
<register mnemonic="SCDR" type="CtrlReg" value="0x0C0E"
size="2">
<description>SCI data register</description>
</register>
<register mnemonic="QPDR" type="CtrlReg" value="0x0C15"
size="2">
<description>QSM port data register</description>
</register>
<register mnemonic="QPAR" type="CtrlReg" value="0x0C16"
size="2">
<description>QSM pin assignment register</description>
</register>
<register mnemonic="QDDR" type="CtrlReg" value="0x0C17"
size="2">
<description>QSM data direction register</description>
</register>
<register mnemonic="SPCR0" type="CtrlReg" value="0x0C18"
size="2">
<description>QSPI control register 0</description>
</register>
<register mnemonic="SPCR1" type="CtrlReg" value="0x0C1A"
size="2">
<description>QSPI control register 1</description>
</register>
<register mnemonic="SPCR2" type="CtrlReg" value="0x0C1C"
size="2">
<description>QSPI control register 2</description>
</register>
<register mnemonic="SPCR3" type="CtrlReg" value="0x0C1E"
size="1">
<description>QSPI control register 3</description>
</register>
<register mnemonic="SPSR" type="CtrlReg" value="0x0C1F"
size="1">
<description>QSPI status register</description>
</register>
<register mnemonic="QRXD" type="CtrlReg" value="0x0D00"
size="2">
<description>QSPI receive data</description>
</register>
<register mnemonic="QTXD" type="CtrlReg" value="0x0D20"
size="2">
<description>QSPI transmit data</description>
</register>
<register mnemonic="QCMD" type="CtrlReg" value="0x0D40"
size="2">
<description>QSPI command control</description>
</register>
</registerGroup>
</registerDefinitions>
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