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- register element attributes added/changed:

Browse Source 
* name -> mnemonic
* altmnemonic
* accessmode
* accessattr
- register dict updated
- Register class redesigned

git-svn-id: https://svn.code.sf.net/p/libusbjava/code/trunk@114 94ad28fe-ef68-46b1-9651-e7ae4fcf1c4c
This commit is contained in:
schlaepfer
2006-03-16 07:47:05 +00:00
parent 751814e2f2
commit 8708aa2e0e
9 changed files with 2052 additions and 477 deletions
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9
mcdp/resources/targets/general/registerDictionary.dtd
View File

@@ -5,14 +5,17 @@
to the specific register used in this registerDict.
-->
<!ELEMENT registerDefinitions ((registerGroup*, register*) | (register*, registerGroup*))>
<!ELEMENT registerDefinitions ((registerGroup* | register*)*)>
<!ELEMENT registerGroup (register+)>
<!ATTLIST registerGroup
baseAddress CDATA #REQUIRED>
<!ELEMENT register (description?)>
<!ATTLIST register
name CDATA #REQUIRED
mnemonic CDATA #REQUIRED
altmnemonic CDATA #IMPLIED
type (type1|type2|type3) #REQUIRED
value CDATA #REQUIRED
size (1|2|4) #REQUIRED>
size (1|2|4) #REQUIRED
accessmode (supervisor|user|test) #IMPLIED
accessattr (readonly|writeonly) #IMPLIED>
<!ELEMENT description (#PCDATA)>

9
mcdp/resources/targets/mc68332/registerDictionary.dtd
View File

@@ -4,14 +4,17 @@
Only the type values are MC68332 specific.
-->
<!ELEMENT registerDefinitions ((registerGroup*, register*) | (register*, registerGroup*))>
<!ELEMENT registerDefinitions ((registerGroup* | register*)*)>
<!ELEMENT registerGroup (register+)>
<!ATTLIST registerGroup
baseAddress CDATA #REQUIRED>
<!ELEMENT register (description?)>
<!ATTLIST register
name CDATA #REQUIRED
mnemonic CDATA #REQUIRED
altmnemonic CDATA #IMPLIED
type (CtrlReg|UserReg|SysReg) #REQUIRED
value CDATA #REQUIRED
size (1|2|4) #REQUIRED>
size (1|2|4) #REQUIRED
accessmode (supervisor|user|test) #IMPLIED
accessattr (readonly|writeonly) #IMPLIED>
<!ELEMENT description (#PCDATA)>

277
mcdp/resources/targets/mc68332/registerDictionary.xml
View File

@@ -5,221 +5,221 @@
<registerDefinitions>
<!-- data registers -->
<register name="D0" type="UserReg" value="0x0" size="4">
<register mnemonic="D0" type="UserReg" value="0x0" size="4">
<description>data register 0</description>
</register>
<register name="D1" type="UserReg" value="0x1" size="4">
<register mnemonic="D1" type="UserReg" value="0x1" size="4">
<description>data register 1</description>
</register>
<register name="D2" type="UserReg" value="0x2" size="4">
<register mnemonic="D2" type="UserReg" value="0x2" size="4">
<description>data register 2</description>
</register>
<register name="D3" type="UserReg" value="3" size="4">
<register mnemonic="D3" type="UserReg" value="3" size="4">
<description>data register 3</description>
</register>
<register name="D4" type="UserReg" value="4" size="4">
<register mnemonic="D4" type="UserReg" value="4" size="4">
<description>data register 43</description>
</register>
<register name="D5" type="UserReg" value="5" size="4">
<register mnemonic="D5" type="UserReg" value="5" size="4">
<description>data register 5</description>
</register>
<register name="D6" type="UserReg" value="6" size="4">
<register mnemonic="D6" type="UserReg" value="6" size="4">
<description>data register 6</description>
</register>
<register name="D7" type="UserReg" value="7" size="4">
<register mnemonic="D7" type="UserReg" value="7" size="4">
<description>data register 7</description>
</register>
<!-- address registers -->
<register name="A0" type="UserReg" value="0x8" size="4">
<register mnemonic="A0" type="UserReg" value="0x8" size="4">
<description>address register 0</description>
</register>
<register name="A1" type="UserReg" value="0x9" size="4">
<register mnemonic="A1" type="UserReg" value="0x9" size="4">
<description>address register 1</description>
</register>
<register name="A2" type="UserReg" value="0xA" size="4">
<register mnemonic="A2" type="UserReg" value="0xA" size="4">
<description>address register 2</description>
</register>
<register name="A3" type="UserReg" value="0xB" size="4">
<register mnemonic="A3" type="UserReg" value="0xB" size="4">
<description>address register 3</description>
</register>
<register name="A4" type="UserReg" value="0xC" size="4">
<register mnemonic="A4" type="UserReg" value="0xC" size="4">
<description>address register 4</description>
</register>
<register name="A5" type="UserReg" value="0xD" size="4">
<register mnemonic="A5" type="UserReg" value="0xD" size="4">
<description>address register 5</description>
</register>
<register name="A6" type="UserReg" value="0xE" size="4">
<register mnemonic="A6" type="UserReg" value="0xE" size="4">
<description>address register 06</description>
</register>
<register name="A7" type="UserReg" value="0xF" size="4">
<register mnemonic="A7" type="UserReg" value="0xF" size="4">
<description>address register 7</description>
</register>
<!-- system registers -->
<register name="RPC" type="SysReg" value="0x0" size="4">
<register mnemonic="RPC" type="SysReg" value="0x0" size="4">
<description>return program counter</description>
</register>
<register name="PCC" type="SysReg" value="0x1" size="4">
<register mnemonic="PCC" type="SysReg" value="0x1" size="4">
<description>current instruction program counter</description>
</register>
<register name="SR" type="SysReg" value="0xB" size="2">
<register mnemonic="SR" type="SysReg" value="0xB" size="2">
<description>status register</description>
</register>
<register name="USP" type="SysReg" value="0xC" size="4">
<register mnemonic="USP" type="SysReg" value="0xC" size="4">
<description>user stack pointer (A7)</description>
</register>
<register name="SSP" type="SysReg" value="0xD" size="4">
<register mnemonic="SSP" type="SysReg" value="0xD" size="4">
<description>supervisor stack pointer</description>
</register>
<register name="SFC" type="SysReg" value="0xE" size="4">
<register mnemonic="SFC" type="SysReg" value="0xE" size="4">
<description>source function code register</description>
</register>
<register name="DFC" type="SysReg" value="0xF" size="4">
<register mnemonic="DFC" type="SysReg" value="0xF" size="4">
<description>destination function code register</description>
</register>
<register name="ATEMP" type="SysReg" value="0x8" size="4">
<register mnemonic="ATEMP" type="SysReg" value="0x8" size="4">
<description>temporary register A</description>
</register>
<register name="FAR" type="SysReg" value="0x9" size="4">
<register mnemonic="FAR" type="SysReg" value="0x9" size="4">
<description>fault address register</description>
</register>
<register name="VBR" type="SysReg" value="0xA" size="4">
<register mnemonic="VBR" type="SysReg" value="0xA" size="4">
<description>vector base register</description>
</register>
<registerGroup baseAddress="0xFFFFF000">
<!-- control registers -->
<register name="SIMCR" type="CtrlReg" value="0x0A00"
<register mnemonic="SIMCR" type="CtrlReg" value="0x0A00"
size="2">
<description>sim module configuration register</description>
</register>
<register name="SYNCR" type="CtrlReg" value="0x0A04"
<register mnemonic="SYNCR" type="CtrlReg" value="0x0A04"
size="2">
<description>clock synthesizer control</description>
</register>
<register name="SYPCR" type="CtrlReg" value="0x0A20"
<register mnemonic="SYPCR" type="CtrlReg" value="0x0A20"
size="2">
<description>system protection control</description>
</register>
<register name="CSPAR0" type="CtrlReg" value="0x0A44"
<register mnemonic="CSPAR0" type="CtrlReg" value="0x0A44"
size="2">
<description>
chip select pin assignment register 0
</description>
</register>
<register name="CSPAR1" type="CtrlReg" value="0x0A46"
<register mnemonic="CSPAR1" type="CtrlReg" value="0x0A46"
size="2">
<description>
chip select pin assignment register 1
</description>
</register>
<register name="CSBARBT" type="CtrlReg" value="0x0A48"
<register mnemonic="CSBARBT" type="CtrlReg" value="0x0A48"
size="2">
<description>CSBOOT base address register</description>
</register>
<register name="CSORBT" type="CtrlReg" value="0x0A4A"
<register mnemonic="CSORBT" type="CtrlReg" value="0x0A4A"
size="2">
<description>CSBOOT option register</description>
</register>
<register name="CSBAR0" type="CtrlReg" value="0x0A4C"
<register mnemonic="CSBAR0" type="CtrlReg" value="0x0A4C"
size="2">
<description>
chip select 0 base address register
</description>
</register>
<register name="CSOR0" type="CtrlReg" value="0x0A4E"
<register mnemonic="CSOR0" type="CtrlReg" value="0x0A4E"
size="2">
<description>chip select 0 option register</description>
</register>
<register name="CSBAR1" type="CtrlReg" value="0x0A50"
<register mnemonic="CSBAR1" type="CtrlReg" value="0x0A50"
size="2">
<description>
chip select 1 base address register
</description>
</register>
<register name="CSOR1" type="CtrlReg" value="0x0A52"
<register mnemonic="CSOR1" type="CtrlReg" value="0x0A52"
size="2">
<description>chip select 1 option register</description>
</register>
<register name="CSBAR2" type="CtrlReg" value="0x0A54"
<register mnemonic="CSBAR2" type="CtrlReg" value="0x0A54"
size="2">
<description>
chip select 2 base address register
</description>
</register>
<register name="CSOR2" type="CtrlReg" value="0x0A56"
<register mnemonic="CSOR2" type="CtrlReg" value="0x0A56"
size="2">
<description>chip select 2 option register</description>
</register>
<register name="CSBAR3" type="CtrlReg" value="0x0A58"
<register mnemonic="CSBAR3" type="CtrlReg" value="0x0A58"
size="2">
<description>
chip select 3 base address register
</description>
</register>
<register name="CSOR3" type="CtrlReg" value="0x0A5A"
<register mnemonic="CSOR3" type="CtrlReg" value="0x0A5A"
size="2">
<description>chip select 3 option register</description>
</register>
<register name="CSBAR4" type="CtrlReg" value="0x0A5C"
<register mnemonic="CSBAR4" type="CtrlReg" value="0x0A5C"
size="2">
<description>
chip select 4 base address register
</description>
</register>
<register name="CSOR4" type="CtrlReg" value="0x0A5E"
<register mnemonic="CSOR4" type="CtrlReg" value="0x0A5E"
size="2">
<description>chip select 4 option register</description>
</register>
<register name="CSBAR5" type="CtrlReg" value="0x0A60"
<register mnemonic="CSBAR5" type="CtrlReg" value="0x0A60"
size="2">
<description>
chip select 5 base address register
</description>
</register>
<register name="CSOR5" type="CtrlReg" value="0x0A62"
<register mnemonic="CSOR5" type="CtrlReg" value="0x0A62"
size="2">
<description>chip select 5 option register</description>
</register>
<register name="CSBAR6" type="CtrlReg" value="0x0A64"
<register mnemonic="CSBAR6" type="CtrlReg" value="0x0A64"
size="2">
<description>
chip select 6 base address register
</description>
</register>
<register name="CSOR6" type="CtrlReg" value="0x0A66"
<register mnemonic="CSOR6" type="CtrlReg" value="0x0A66"
size="2">
<description>chip select 6 option register</description>
</register>
<register name="CSBAR7" type="CtrlReg" value="0x0A68"
<register mnemonic="CSBAR7" type="CtrlReg" value="0x0A68"
size="2">
<description>
chip select 7 base address register
</description>
</register>
<register name="CSOR7" type="CtrlReg" value="0x0A6A"
<register mnemonic="CSOR7" type="CtrlReg" value="0x0A6A"
size="2">
<description>chip select 7 option register</description>
</register>
<register name="CSBAR8" type="CtrlReg" value="0x0A6C"
<register mnemonic="CSBAR8" type="CtrlReg" value="0x0A6C"
size="2">
<description>
chip select 8 base address register
</description>
</register>
<register name="CSOR8" type="CtrlReg" value="0x0A6E"
<register mnemonic="CSOR8" type="CtrlReg" value="0x0A6E"
size="2">
<description>chip select 8 option register</description>
</register>
<register name="CSBAR9" type="CtrlReg" value="0x0A70"
<register mnemonic="CSBAR9" type="CtrlReg" value="0x0A70"
size="2">
<description>
chip select 9 base address register
</description>
</register>
<register name="CSOR9" type="CtrlReg" value="0x0A72"
<register mnemonic="CSOR9" type="CtrlReg" value="0x0A72"
size="2">
<description>chip select 9 option register</description>
</register>
@@ -227,258 +227,297 @@
<!-- TPU registers -->
<!-- adjust the setting of tpumcr to reflect modmap bit -->
<register name="TRAMMCR" type="CtrlReg" value="0x0B00"
<register mnemonic="TRAMMCR" type="CtrlReg" value="0x0B00"
size="2">
<description>
TPURAM module configuration register
</description>
</register>
<register name="TRAMBAR" type="CtrlReg" value="0x0B04"
<register mnemonic="TRAMBAR" type="CtrlReg" value="0x0B04"
size="2">
<description>
TPURAM base address and status register
</description>
</register>
<register name="TPUMCR" type="CtrlReg" value="0x0E00"
<register mnemonic="TPUMCR" type="CtrlReg" value="0x0E00"
size="2">
<description>TPU module control register</description>
</register>
<register name="TPUCFG" type="CtrlReg" value="0x0E02"
<register mnemonic="TPUCFG" type="CtrlReg" value="0x0E02"
size="2">
<description>TPU configuration register</description>
</register>
<register name="DSCR" type="CtrlReg" value="0x0E04" size="2">
<register mnemonic="DSCR" type="CtrlReg" value="0x0E04"
size="2">
<description>
development support control register
</description>
</register>
<register name="DSSR" type="CtrlReg" value="0x0E06" size="2">
<register mnemonic="DSSR" type="CtrlReg" value="0x0E06"
size="2">
<description>
development support status register
</description>
</register>
<register name="TPUICR" type="CtrlReg" value="0x0E08"
<register mnemonic="TPUICR" type="CtrlReg" value="0x0E08"
size="2">
<description>
TPU interrupt configuration register
</description>
</register>
<register name="TPUIER" type="CtrlReg" value="0x0E0A"
<register mnemonic="TPUIER" type="CtrlReg" value="0x0E0A"
size="2">
<description>TPU interrupt enable register</description>
</register>
<register name="CFSR0" type="CtrlReg" value="0x0E0C"
<register mnemonic="CFSR0" type="CtrlReg" value="0x0E0C"
size="2">
<description>
channel function select register 0
</description>
</register>
<register name="CFSR1" type="CtrlReg" value="0x0E0E"
<register mnemonic="CFSR1" type="CtrlReg" value="0x0E0E"
size="2">
<description>
channel function select register 1
</description>
</register>
<register name="CFSR2" type="CtrlReg" value="0x0E10"
<register mnemonic="CFSR2" type="CtrlReg" value="0x0E10"
size="2">
<description>
channel function select register 2
</description>
</register>
<register name="CFSR3" type="CtrlReg" value="0x0E12"
<register mnemonic="CFSR3" type="CtrlReg" value="0x0E12"
size="2">
<description>
channel function select register 3
</description>
</register>
<register name="HSR0" type="CtrlReg" value="0x0E14" size="2">
<register mnemonic="HSR0" type="CtrlReg" value="0x0E14"
size="2">
<description>host sequence register 0</description>
</register>
<register name="HSR1" type="CtrlReg" value="0x0E16" size="2">
<register mnemonic="HSR1" type="CtrlReg" value="0x0E16"
size="2">
<description>host sequence register 1</description>
</register>
<register name="HSRR0" type="CtrlReg" value="0x0E18"
<register mnemonic="HSRR0" type="CtrlReg" value="0x0E18"
size="2">
<description>host service request register 0</description>
</register>
<register name="HSRR1" type="CtrlReg" value="0x0E1A"
<register mnemonic="HSRR1" type="CtrlReg" value="0x0E1A"
size="2">
<description>host service request register 1</description>
</register>
<register name="CPR0" type="CtrlReg" value="0x0E1C" size="2">
<register mnemonic="CPR0" type="CtrlReg" value="0x0E1C"
size="2">
<description>channel priority register 0</description>
</register>
<register name="CPR1" type="CtrlReg" value="0x0E1E" size="2">
<register mnemonic="CPR1" type="CtrlReg" value="0x0E1E"
size="2">
<description>channel priority register 1</description>
</register>
<register name="TPUISR" type="CtrlReg" value="0x0E20"
<register mnemonic="TPUISR" type="CtrlReg" value="0x0E20"
size="2">
<description>TPU interrupt status register</description>
</register>
<register name="LINK" type="CtrlReg" value="0x0E22" size="2">
<register mnemonic="LINK" type="CtrlReg" value="0x0E22"
size="2">
<description>???</description>
</register>
<register name="SGLR" type="CtrlReg" value="0x0E24" size="2">
<register mnemonic="SGLR" type="CtrlReg" value="0x0E24"
size="2">
<description>service grant latch register</description>
</register>
<register name="DCNR" type="CtrlReg" value="0x0E26" size="2">
<register mnemonic="DCNR" type="CtrlReg" value="0x0E26"
size="2">
<description>decoded channel number register</description>
</register>
<!-- Port E Registers -->
<register name="PORTE0" type="CtrlReg" value="0x0A11"
<register mnemonic="PORTE0" type="CtrlReg" value="0x0A11"
size="1">
<description>Port E data register 0</description>
</register>
<register name="PORTE1" type="CtrlReg" value="0x0A13"
<register mnemonic="PORTE1" type="CtrlReg" value="0x0A13"
size="1">
<description>Port E data register 1</description>
</register>
<register name="DDRE" type="CtrlReg" value="0x0A15" size="1">
<register mnemonic="DDRE" type="CtrlReg" value="0x0A15"
size="1">
<description>Port E data direction register</description>
</register>
<register name="PEPAR" type="CtrlReg" value="0x0A17"
<register mnemonic="PEPAR" type="CtrlReg" value="0x0A17"
size="1">
<description>Port E pin assignment register</description>
</register>
<!-- Port F Registers -->
<register name="PORTF0" type="CtrlReg" value="0x0A19"
<register mnemonic="PORTF0" type="CtrlReg" value="0x0A19"
size="1">
<description>Port F data register 0</description>
</register>
<register name="PORTF1" type="CtrlReg" value="0x0A1B"
<register mnemonic="PORTF1" type="CtrlReg" value="0x0A1B"
size="1">
<description>Port F data register 1</description>
</register>
<register name="DDRF" type="CtrlReg" value="0x0A1D" size="1">
<register mnemonic="DDRF" type="CtrlReg" value="0x0A1D"
size="1">
<description>Port F data direction register</description>
</register>
<register name="PFPAR" type="CtrlReg" value="0x0A1F"
<register mnemonic="PFPAR" type="CtrlReg" value="0x0A1F"
size="1">
<description>Port F pin assignment register</description>
</register>
<!-- TPU parameter ram start addresses -->
<register name="CH0" type="CtrlReg" value="0x0F00" size="2">
<register mnemonic="CH0" type="CtrlReg" value="0x0F00"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH1" type="CtrlReg" value="0x0F10" size="2">
<register mnemonic="CH1" type="CtrlReg" value="0x0F10"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH2" type="CtrlReg" value="0x0F20" size="2">
<register mnemonic="CH2" type="CtrlReg" value="0x0F20"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH3" type="CtrlReg" value="0x0F30" size="2">
<register mnemonic="CH3" type="CtrlReg" value="0x0F30"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH4" type="CtrlReg" value="0x0F40" size="2">
<register mnemonic="CH4" type="CtrlReg" value="0x0F40"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH5" type="CtrlReg" value="0x0F50" size="2">
<register mnemonic="CH5" type="CtrlReg" value="0x0F50"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH6" type="CtrlReg" value="0x0F60" size="2">
<register mnemonic="CH6" type="CtrlReg" value="0x0F60"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH7" type="CtrlReg" value="0x0F70" size="2">
<register mnemonic="CH7" type="CtrlReg" value="0x0F70"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH8" type="CtrlReg" value="0x0F80" size="2">
<register mnemonic="CH8" type="CtrlReg" value="0x0F80"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH9" type="CtrlReg" value="0x0F90" size="2">
<register mnemonic="CH9" type="CtrlReg" value="0x0F90"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH10" type="CtrlReg" value="0x0FA0" size="2">
<register mnemonic="CH10" type="CtrlReg" value="0x0FA0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH11" type="CtrlReg" value="0x0FB0" size="2">
<register mnemonic="CH11" type="CtrlReg" value="0x0FB0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH12" type="CtrlReg" value="0x0FC0" size="2">
<register mnemonic="CH12" type="CtrlReg" value="0x0FC0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH13" type="CtrlReg" value="0x0FD0" size="2">
<register mnemonic="CH13" type="CtrlReg" value="0x0FD0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH14" type="CtrlReg" value="0x0FE0" size="2">
<register mnemonic="CH14" type="CtrlReg" value="0x0FE0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<register name="CH15" type="CtrlReg" value="0x0FF0" size="2">
<register mnemonic="CH15" type="CtrlReg" value="0x0FF0"
size="2">
<description>TPU parameter ram start address</description>
</register>
<!-- queued serial module -->
<register name="QMCR" type="CtrlReg" value="0x0C00" size="2">
<register mnemonic="QMCR" type="CtrlReg" value="0x0C00"
size="2">
<description>QSM configuration register</description>
</register>
<register name="QTEST" type="CtrlReg" value="0x0C02"
<register mnemonic="QTEST" type="CtrlReg" value="0x0C02"
size="2">
<description>QSM test register</description>
</register>
<register name="QILR" type="CtrlReg" value="0x0C04" size="1">
<register mnemonic="QILR" type="CtrlReg" value="0x0C04"
size="1">
<description>QSM interrupt level register</description>
</register>
<register name="QIVR" type="CtrlReg" value="0x0C05" size="1">
<register mnemonic="QIVR" type="CtrlReg" value="0x0C05"
size="1">
<description>QSM interrupt vector register</description>
</register>
<register name="SCCR0" type="CtrlReg" value="0x0C08"
<register mnemonic="SCCR0" type="CtrlReg" value="0x0C08"
size="2">
<description>SCI control register 0</description>
</register>
<register name="SCCR1" type="CtrlReg" value="0x0C0A"
<register mnemonic="SCCR1" type="CtrlReg" value="0x0C0A"
size="2">
<description>SCI control register 1</description>
</register>
<register name="SCSR" type="CtrlReg" value="0x0C0C" size="2">
<register mnemonic="SCSR" type="CtrlReg" value="0x0C0C"
size="2">
<description>SCI status register</description>
</register>
<register name="SCDR" type="CtrlReg" value="0x0C0E" size="2">
<register mnemonic="SCDR" type="CtrlReg" value="0x0C0E"
size="2">
<description>SCI data register</description>
</register>
<register name="QPDR" type="CtrlReg" value="0x0C15" size="2">
<register mnemonic="QPDR" type="CtrlReg" value="0x0C15"
size="2">
<description>QSM port data register</description>
</register>
<register name="QPAR" type="CtrlReg" value="0x0C16" size="2">
<register mnemonic="QPAR" type="CtrlReg" value="0x0C16"
size="2">
<description>QSM pin assignment register</description>
</register>
<register name="QDDR" type="CtrlReg" value="0x0C17" size="2">
<register mnemonic="QDDR" type="CtrlReg" value="0x0C17"
size="2">
<description>QSM data direction register</description>
</register>
<register name="SPCR0" type="CtrlReg" value="0x0C18"
<register mnemonic="SPCR0" type="CtrlReg" value="0x0C18"
size="2">
<description>QSPI control register 0</description>
</register>
<register name="SPCR1" type="CtrlReg" value="0x0C1A"
<register mnemonic="SPCR1" type="CtrlReg" value="0x0C1A"
size="2">
<description>QSPI control register 1</description>
</register>
<register name="SPCR2" type="CtrlReg" value="0x0C1C"
<register mnemonic="SPCR2" type="CtrlReg" value="0x0C1C"
size="2">
<description>QSPI control register 2</description>
</register>
<register name="SPCR3" type="CtrlReg" value="0x0C1E"
<register mnemonic="SPCR3" type="CtrlReg" value="0x0C1E"
size="1">
<description>QSPI control register 3</description>
</register>
<register name="SPSR" type="CtrlReg" value="0x0C1F" size="1">
<register mnemonic="SPSR" type="CtrlReg" value="0x0C1F"
size="1">
<description>QSPI status register</description>
</register>
<register name="QRXD" type="CtrlReg" value="0x0D00" size="2">
<register mnemonic="QRXD" type="CtrlReg" value="0x0D00"
size="2">
<description>QSPI receive data</description>
</register>
<register name="QTXD" type="CtrlReg" value="0x0D20" size="2">
<register mnemonic="QTXD" type="CtrlReg" value="0x0D20"
size="2">
<description>QSPI transmit data</description>
</register>
<register name="QCMD" type="CtrlReg" value="0x0D40" size="2">
<register mnemonic="QCMD" type="CtrlReg" value="0x0D40"
size="2">
<description>QSPI command control</description>
</register>
</registerGroup>

9
mcdp/resources/targets/mpc555/registerDictionary.dtd
View File

@@ -4,14 +4,17 @@
Only the type values are MPC555 specific.
-->
<!ELEMENT registerDefinitions ((registerGroup*, register*) | (register*, registerGroup*))>
<!ELEMENT registerDefinitions ((registerGroup* | register*)*)>
<!ELEMENT registerGroup (register+)>
<!ATTLIST registerGroup
baseAddress CDATA #REQUIRED>
<!ELEMENT register (description?)>
<!ATTLIST register
name CDATA #REQUIRED
mnemonic CDATA #REQUIRED
altmnemonic CDATA #IMPLIED
type (CtrlReg|GPR|FPR|SPR|MSR|CR|FPSCR) #REQUIRED
value CDATA #REQUIRED
size (1|2|4) #REQUIRED>
size (1|2|4) #REQUIRED
accessmode (supervisor|user|test) #IMPLIED
accessattr (readonly|writeonly) #IMPLIED>
<!ELEMENT description (#PCDATA)>

2045
mcdp/resources/targets/mpc555/registerDictionary.xml
View File

File diff suppressed because it is too large Load Diff

147
mcdp/src/ch/ntb/mcdp/dict/Register.java
View File

@@ -7,6 +7,8 @@ package ch.ntb.mcdp.dict;
*/
public abstract class Register {
private static final String INIT_STRING = "***";
/**
* Register specific type values. <br>
* The index of each type in the types array represents its numeric value.
@@ -19,59 +21,154 @@ public abstract class Register {
protected static String[] types = null;
/**
* Name of the register. Registers are identified by this value.
* Menemoic of the register. Registers are identified by this value.
*/
public String name = "NOT INITIALISED";
private String mnemonic = INIT_STRING;
/**
* Alternative mnemonic of the register
*/
private String altmnemonic = INIT_STRING;
/**
* Register specific type
*/
public int type;
private int type;
/**
* Address or a register specific value (e.g. BDI-identifier)
*/
public int value;
private int value;
/**
* Size in bytes (width)
*/
public int size;
private int size;
/**
* A string description of the register
*/
public String description;
private String description;
/**
* @param name
* name of the register. Registers are identified by this value.
* @param type
* register specific type
* @param value
* address or a register specific value (e.g. BDI-identifier)
* @param size
* size in bytes
* @param description
* a string description of the register
* @return the mnemonic of this register
*/
public void init(String name, int type, int value, int size,
String description) {
this.name = name;
this.type = type;
this.value = value;
this.size = size;
public String getMnemonic() {
return mnemonic;
}
/**
* Set the mnemonic of this register
*
* @param name
*/
public void setMnemonic(String name) {
this.mnemonic = name;
}
/**
* @return alternative mnemonic of the register
*/
public String getAltmnemonic() {
return altmnemonic;
}
/**
* Set the alternative name of the register.
*
* @param altname
*/
public void setAltmnemonic(String altname) {
this.altmnemonic = altname;
}
/**
* @return the register description
*/
public String getDescription() {
return description;
}
/**
* Set the register description.
*
* @param description
*/
public void setDescription(String description) {
this.description = description;
}
/**
* @return the size in bytes (width)
*/
public int getSize() {
return size;
}
/**
* Set the size in bytes (width)
*
* @param size
*/
public void setSize(int size) {
this.size = size;
}
/**
* @return the type of the register. This is the index of the static
* <code>types</code> String array.
*/
public int getType() {
return type;
}
/**
* Set the type of the register. This is the index of the static
* <code>types</code> String array.
*
* @param type
*/
public void setType(int type) {
this.type = type;
}
/**
* @return the address or a register specific value (e.g. BDI-identifier)
*/
public int getValue() {
return value;
}
/**
* Set the address or a register specific value (e.g. BDI-identifier).
*
* @param value
*/
public void setValue(int value) {
this.value = value;
}
/**
* @return true if a mnemonic was set and the size is valid (size > 0), else
* false
*/
public boolean isValid() {
if ((mnemonic == INIT_STRING) || (size <= 0))
return false;
return true;
}
@Override
public String toString() {
return new String(name + "\t" + types[type] + "\t0x"
+ Integer.toHexString(value) + "\t" + size + "\t" + description);
return new String(mnemonic + "\t" + altmnemonic + "\t" + types[type]
+ "\t0x" + Integer.toHexString(value) + "\t" + size + "\t"
+ description);
}
/**
* Get the register specific type strings.
* Get the register specific type strings. This value has to be initialised
* in the <code>static</code> section of the derived Register class as
* this is Register specific.
*
* @return types strings
*/

21
mcdp/src/ch/ntb/mcdp/dict/RegisterDict.java
View File

@@ -52,7 +52,7 @@ public abstract class RegisterDict {
private static final String DESCRIPTION = "description";
private static final String REG_ATTR_NAME = "name";
private static final String REG_ATTR_MNEMONIC = "mnemonic";
private static final String REG_ATTR_TYPE = "type";
@@ -104,16 +104,22 @@ public abstract class RegisterDict {
String description) {
// remove before add for updates
for (Iterator i = registers.iterator(); i.hasNext();) {
if (((Register) i.next()).name.equals(name)) {
Register r = (Register) i.next();
if (r.getMnemonic().equals(name) || r.getAltmnemonic().equals(name)) {
i.remove();
}
}
Register reg = null;
try {
reg = (Register) regClass.newInstance();
reg.init(name, type, value, size, description);
reg.setMnemonic(name);
reg.setType(type);
reg.setValue(value);
reg.setSize(size);
reg.setDescription(description);
} catch (Exception e) {
e.printStackTrace();
// TODO exception handling
System.exit(1);
}
registers.add(reg);
@@ -149,7 +155,7 @@ public abstract class RegisterDict {
public Register getRegister(String name) {
for (Iterator i = registers.iterator(); i.hasNext();) {
Register r = (Register) i.next();
if (r.name.equals(name)) {
if (r.getMnemonic().equals(name) || r.getAltmnemonic().equals(name)) {
return r;
}
}
@@ -162,7 +168,8 @@ public abstract class RegisterDict {
public void printRegisters() {
System.out
.println("******************** register dictionary *********************");
System.out.println("Name\tType\tAddress\tSize\tDescription");
System.out
.println("Mnemonic\tAltmnemonic\tType\tAddress\tSize\tDescription");
System.out
.println("**************************************************************");
for (Iterator i = registers.iterator(); i.hasNext();) {
@@ -235,7 +242,7 @@ public abstract class RegisterDict {
} else if (list.item(j).getNodeName().equals(REGISTER)) {
NamedNodeMap attributes = list.item(j).getAttributes();
// attributes: name, type, offset, size
Node n = attributes.getNamedItem(REG_ATTR_NAME);
Node n = attributes.getNamedItem(REG_ATTR_MNEMONIC);
String name = n.getNodeValue();
n = attributes.getNamedItem(REG_ATTR_TYPE);
String typeStr = n.getNodeValue();
@@ -266,7 +273,7 @@ public abstract class RegisterDict {
if (list.item(i).getNodeName().equals(REGISTER)) {
NamedNodeMap attributes = list.item(i).getAttributes();
// attributes: name, type, offset, size
Node n = attributes.getNamedItem(REG_ATTR_NAME);
Node n = attributes.getNamedItem(REG_ATTR_MNEMONIC);
String name = n.getNodeValue();
n = attributes.getNamedItem(REG_ATTR_TYPE);
String typeStr = n.getNodeValue();

6
mcdp/src/ch/ntb/mcdp/mc68332/MC68332Register.java
View File

@@ -3,11 +3,15 @@ package ch.ntb.mcdp.mc68332;
import ch.ntb.mcdp.dict.Register;
/**
* Representation of a MC68332 Register
*
* For system and user registers the <code>value</code> value is used as BDI
* specific identifier (code specific to each register from the Technical
* Reference Manual).
*
* @author schlaepfer
*
*/
public class MC68332Register extends Register {
// Register Types

6
mcdp/src/ch/ntb/mcdp/mpc555/MPC555Register.java
View File

@@ -2,6 +2,12 @@ package ch.ntb.mcdp.mpc555;
import ch.ntb.mcdp.dict.Register;
/**
* Representation of a MPC555 Register
*
* @author schlaepfer
*
*/
public class MPC555Register extends Register {
// Register Types