- support for 555 added
- all 332 registers moved to xml-file - dtd updated for registerGroup + registers without group git-svn-id: https://svn.code.sf.net/p/libusbjava/code/trunk@50 94ad28fe-ef68-46b1-9651-e7ae4fcf1c4c
This commit is contained in:
schlaepfer
@@ -1,8 +1,10 @@
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<?xml version='1.0' encoding='utf-8'?>
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<!-- DTD for a RegisterDictionary. -->
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<!-- DTD for MC68332 RegisterDictionary.
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Only the type values are MC68332 specific.
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-->
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<!ELEMENT registerDefinitions (registerGroup+)>
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<!ELEMENT registerDefinitions ((registerGroup*, register*) | (register*, registerGroup*))>
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<!ELEMENT registerGroup (register+)>
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<!ATTLIST registerGroup
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baseAddress CDATA #REQUIRED>
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@@ -10,6 +12,6 @@
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<!ATTLIST register
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name CDATA #REQUIRED
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type (CtrlReg|UserReg|SysReg) #REQUIRED
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offset CDATA #REQUIRED
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value CDATA #REQUIRED
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size (1|2|4) #REQUIRED>
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<!ELEMENT description (#PCDATA)>
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@@ -4,118 +4,222 @@
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<!DOCTYPE registerDefinitions SYSTEM "registerDictionary.dtd">
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<registerDefinitions>
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<!-- data registers -->
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<register name="D0" type="UserReg" value="0x0" size="4">
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<description>data register 0</description>
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</register>
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<register name="D1" type="UserReg" value="0x1" size="4">
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<description>data register 1</description>
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</register>
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<register name="D2" type="UserReg" value="0x2" size="4">
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<description>data register 2</description>
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</register>
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<register name="D3" type="UserReg" value="3" size="4">
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<description>data register 3</description>
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</register>
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<register name="D4" type="UserReg" value="4" size="4">
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<description>data register 43</description>
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</register>
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<register name="D5" type="UserReg" value="5" size="4">
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<description>data register 5</description>
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</register>
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<register name="D6" type="UserReg" value="6" size="4">
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<description>data register 6</description>
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</register>
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<register name="D7" type="UserReg" value="7" size="4">
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<description>data register 7</description>
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</register>
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<!-- address registers -->
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<register name="A0" type="UserReg" value="0x8" size="4">
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<description>address register 0</description>
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</register>
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<register name="A1" type="UserReg" value="0x9" size="4">
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<description>address register 1</description>
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</register>
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<register name="A2" type="UserReg" value="0xA" size="4">
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<description>address register 2</description>
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</register>
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<register name="A3" type="UserReg" value="0xB" size="4">
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<description>address register 3</description>
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</register>
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<register name="A4" type="UserReg" value="0xC" size="4">
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<description>address register 4</description>
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</register>
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<register name="A5" type="UserReg" value="0xD" size="4">
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<description>address register 5</description>
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</register>
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<register name="A6" type="UserReg" value="0xE" size="4">
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<description>address register 06</description>
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</register>
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<register name="A7" type="UserReg" value="0xF" size="4">
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<description>address register 7</description>
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</register>
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<!-- system registers -->
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<register name="RPC" type="SysReg" value="0x0" size="4">
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<description>return program counter</description>
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</register>
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<register name="PCC" type="SysReg" value="0x1" size="4">
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<description>current instruction program counter</description>
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</register>
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<register name="SR" type="SysReg" value="0xB" size="2">
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<description>status register</description>
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</register>
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<register name="USP" type="SysReg" value="0xC" size="4">
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<description>user stack pointer (A7)</description>
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</register>
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<register name="SSP" type="SysReg" value="0xD" size="4">
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<description>supervisor stack pointer</description>
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</register>
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<register name="SFC" type="SysReg" value="0xE" size="4">
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<description>source function code register</description>
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</register>
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<register name="DFC" type="SysReg" value="0xF" size="4">
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<description>destination function code register</description>
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</register>
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<register name="ATEMP" type="SysReg" value="0x8" size="4">
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<description>temporary register A</description>
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</register>
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<register name="FAR" type="SysReg" value="0x9" size="4">
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<description>fault address register</description>
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</register>
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<register name="VBR" type="SysReg" value="0xA" size="4">
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<description>vector base register</description>
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</register>
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<registerGroup baseAddress="0xFFFFF000">
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<!-- control registers -->
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<register name="SIMCR" type="CtrlReg" offset="0x0A00"
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<register name="SIMCR" type="CtrlReg" value="0x0A00"
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size="2">
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<description>sim module configuration register</description>
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</register>
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<register name="SYNCR" type="CtrlReg" offset="0x0A04"
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<register name="SYNCR" type="CtrlReg" value="0x0A04"
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size="2">
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<description>clock synthesizer control</description>
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</register>
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<register name="SYPCR" type="CtrlReg" offset="0x0A20"
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<register name="SYPCR" type="CtrlReg" value="0x0A20"
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size="2">
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<description>system protection control</description>
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</register>
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<register name="CSPAR0" type="CtrlReg" offset="0x0A44"
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<register name="CSPAR0" type="CtrlReg" value="0x0A44"
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size="2">
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<description>
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chip select pin assignment register 0
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</description>
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</register>
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<register name="CSPAR1" type="CtrlReg" offset="0x0A46"
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<register name="CSPAR1" type="CtrlReg" value="0x0A46"
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size="2">
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<description>
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chip select pin assignment register 1
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</description>
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</register>
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<register name="CSBARBT" type="CtrlReg" offset="0x0A48"
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<register name="CSBARBT" type="CtrlReg" value="0x0A48"
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size="2">
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<description>CSBOOT base address register</description>
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</register>
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<register name="CSORBT" type="CtrlReg" offset="0x0A4A"
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<register name="CSORBT" type="CtrlReg" value="0x0A4A"
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size="2">
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<description>CSBOOT option register</description>
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</register>
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<register name="CSBAR0" type="CtrlReg" offset="0x0A4C"
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<register name="CSBAR0" type="CtrlReg" value="0x0A4C"
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size="2">
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<description>chip select 0 base address register</description>
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<description>
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chip select 0 base address register
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</description>
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</register>
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<register name="CSOR0" type="CtrlReg" offset="0x0A4E"
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<register name="CSOR0" type="CtrlReg" value="0x0A4E"
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size="2">
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<description>chip select 0 option register</description>
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</register>
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<register name="CSBAR1" type="CtrlReg" offset="0x0A50"
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<register name="CSBAR1" type="CtrlReg" value="0x0A50"
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size="2">
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<description>chip select 1 base address register</description>
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<description>
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chip select 1 base address register
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</description>
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</register>
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<register name="CSOR1" type="CtrlReg" offset="0x0A52"
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<register name="CSOR1" type="CtrlReg" value="0x0A52"
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size="2">
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<description>chip select 1 option register</description>
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</register>
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<register name="CSBAR2" type="CtrlReg" offset="0x0A54"
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<register name="CSBAR2" type="CtrlReg" value="0x0A54"
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size="2">
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<description>chip select 2 base address register</description>
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<description>
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chip select 2 base address register
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</description>
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</register>
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<register name="CSOR2" type="CtrlReg" offset="0x0A56"
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<register name="CSOR2" type="CtrlReg" value="0x0A56"
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size="2">
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<description>chip select 2 option register</description>
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</register>
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<register name="CSBAR3" type="CtrlReg" offset="0x0A58"
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<register name="CSBAR3" type="CtrlReg" value="0x0A58"
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size="2">
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<description>chip select 3 base address register</description>
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<description>
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chip select 3 base address register
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</description>
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</register>
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<register name="CSOR3" type="CtrlReg" offset="0x0A5A"
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<register name="CSOR3" type="CtrlReg" value="0x0A5A"
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size="2">
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<description>chip select 3 option register</description>
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</register>
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<register name="CSBAR4" type="CtrlReg" offset="0x0A5C"
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<register name="CSBAR4" type="CtrlReg" value="0x0A5C"
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size="2">
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<description>chip select 4 base address register</description>
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<description>
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chip select 4 base address register
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</description>
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</register>
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<register name="CSOR4" type="CtrlReg" offset="0x0A5E"
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<register name="CSOR4" type="CtrlReg" value="0x0A5E"
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size="2">
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<description>chip select 4 option register</description>
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</register>
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<register name="CSBAR5" type="CtrlReg" offset="0x0A60"
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<register name="CSBAR5" type="CtrlReg" value="0x0A60"
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size="2">
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<description>chip select 5 base address register</description>
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<description>
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chip select 5 base address register
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</description>
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</register>
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<register name="CSOR5" type="CtrlReg" offset="0x0A62"
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<register name="CSOR5" type="CtrlReg" value="0x0A62"
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size="2">
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<description>chip select 5 option register</description>
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</register>
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<register name="CSBAR6" type="CtrlReg" offset="0x0A64"
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<register name="CSBAR6" type="CtrlReg" value="0x0A64"
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size="2">
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<description>chip select 6 base address register</description>
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<description>
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chip select 6 base address register
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</description>
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</register>
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<register name="CSOR6" type="CtrlReg" offset="0x0A66"
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<register name="CSOR6" type="CtrlReg" value="0x0A66"
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size="2">
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<description>chip select 6 option register</description>
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</register>
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<register name="CSBAR7" type="CtrlReg" offset="0x0A68"
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<register name="CSBAR7" type="CtrlReg" value="0x0A68"
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size="2">
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<description>chip select 7 base address register</description>
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<description>
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chip select 7 base address register
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</description>
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</register>
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<register name="CSOR7" type="CtrlReg" offset="0x0A6A"
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<register name="CSOR7" type="CtrlReg" value="0x0A6A"
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size="2">
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<description>chip select 7 option register</description>
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</register>
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<register name="CSBAR8" type="CtrlReg" offset="0x0A6C"
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<register name="CSBAR8" type="CtrlReg" value="0x0A6C"
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size="2">
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<description>chip select 8 base address register</description>
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<description>
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chip select 8 base address register
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</description>
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</register>
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<register name="CSOR8" type="CtrlReg" offset="0x0A6E"
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<register name="CSOR8" type="CtrlReg" value="0x0A6E"
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size="2">
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<description>chip select 8 option register</description>
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</register>
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<register name="CSBAR9" type="CtrlReg" offset="0x0A70"
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<register name="CSBAR9" type="CtrlReg" value="0x0A70"
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size="2">
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<description>chip select 9 base address register</description>
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<description>
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chip select 9 base address register
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</description>
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</register>
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<register name="CSOR9" type="CtrlReg" offset="0x0A72"
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<register name="CSOR9" type="CtrlReg" value="0x0A72"
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size="2">
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<description>chip select 9 option register</description>
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</register>
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@@ -123,279 +227,258 @@
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<!-- TPU registers -->
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<!-- adjust the setting of tpumcr to reflect modmap bit -->
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<register name="TRAMMCR" type="CtrlReg" offset="0x0B00"
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<register name="TRAMMCR" type="CtrlReg" value="0x0B00"
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size="2">
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<description>TPURAM module configuration register</description>
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<description>
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TPURAM module configuration register
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</description>
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</register>
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<register name="TRAMBAR" type="CtrlReg" offset="0x0B04"
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<register name="TRAMBAR" type="CtrlReg" value="0x0B04"
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size="2">
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<description>TPURAM base address and status register</description>
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<description>
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TPURAM base address and status register
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</description>
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</register>
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<register name="TPUMCR" type="CtrlReg" offset="0x0E00"
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<register name="TPUMCR" type="CtrlReg" value="0x0E00"
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size="2">
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<description>TPU module control register</description>
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</register>
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<register name="TPUCFG" type="CtrlReg" offset="0x0E02"
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<register name="TPUCFG" type="CtrlReg" value="0x0E02"
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size="2">
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<description>TPU configuration register</description>
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</register>
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<register name="DSCR" type="CtrlReg" offset="0x0E04"
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size="2">
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<description>development support control register</description>
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<register name="DSCR" type="CtrlReg" value="0x0E04" size="2">
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<description>
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development support control register
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</description>
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</register>
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<register name="DSSR" type="CtrlReg" offset="0x0E06"
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size="2">
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<description>development support status register</description>
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<register name="DSSR" type="CtrlReg" value="0x0E06" size="2">
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<description>
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development support status register
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</description>
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</register>
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<register name="TPUICR" type="CtrlReg" offset="0x0E08"
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<register name="TPUICR" type="CtrlReg" value="0x0E08"
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size="2">
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<description>TPU interrupt configuration register</description>
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<description>
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TPU interrupt configuration register
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</description>
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</register>
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<register name="TPUIER" type="CtrlReg" offset="0x0E0A"
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<register name="TPUIER" type="CtrlReg" value="0x0E0A"
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size="2">
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<description>TPU interrupt enable register</description>
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</register>
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<register name="CFSR0" type="CtrlReg" offset="0x0E0C"
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<register name="CFSR0" type="CtrlReg" value="0x0E0C"
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size="2">
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<description>channel function select register 0</description>
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<description>
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channel function select register 0
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</description>
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</register>
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<register name="CFSR1" type="CtrlReg" offset="0x0E0E"
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<register name="CFSR1" type="CtrlReg" value="0x0E0E"
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size="2">
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<description>channel function select register 1</description>
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<description>
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channel function select register 1
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</description>
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</register>
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<register name="CFSR2" type="CtrlReg" offset="0x0E10"
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<register name="CFSR2" type="CtrlReg" value="0x0E10"
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size="2">
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<description>channel function select register 2</description>
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<description>
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channel function select register 2
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</description>
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</register>
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<register name="CFSR3" type="CtrlReg" offset="0x0E12"
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<register name="CFSR3" type="CtrlReg" value="0x0E12"
|
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size="2">
|
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<description>channel function select register 3</description>
|
||||
<description>
|
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channel function select register 3
|
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</description>
|
||||
</register>
|
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<register name="HSR0" type="CtrlReg" offset="0x0E14"
|
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size="2">
|
||||
<register name="HSR0" type="CtrlReg" value="0x0E14" size="2">
|
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<description>host sequence register 0</description>
|
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</register>
|
||||
<register name="HSR1" type="CtrlReg" offset="0x0E16"
|
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size="2">
|
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<register name="HSR1" type="CtrlReg" value="0x0E16" size="2">
|
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<description>host sequence register 1</description>
|
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</register>
|
||||
<register name="HSRR0" type="CtrlReg" offset="0x0E18"
|
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<register name="HSRR0" type="CtrlReg" value="0x0E18"
|
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size="2">
|
||||
<description>host service request register 0</description>
|
||||
</register>
|
||||
<register name="HSRR1" type="CtrlReg" offset="0x0E1A"
|
||||
<register name="HSRR1" type="CtrlReg" value="0x0E1A"
|
||||
size="2">
|
||||
<description>host service request register 1</description>
|
||||
</register>
|
||||
<register name="CPR0" type="CtrlReg" offset="0x0E1C"
|
||||
size="2">
|
||||
<register name="CPR0" type="CtrlReg" value="0x0E1C" size="2">
|
||||
<description>channel priority register 0</description>
|
||||
</register>
|
||||
<register name="CPR1" type="CtrlReg" offset="0x0E1E"
|
||||
size="2">
|
||||
<register name="CPR1" type="CtrlReg" value="0x0E1E" size="2">
|
||||
<description>channel priority register 1</description>
|
||||
</register>
|
||||
<register name="TPUISR" type="CtrlReg" offset="0x0E20"
|
||||
<register name="TPUISR" type="CtrlReg" value="0x0E20"
|
||||
size="2">
|
||||
<description>TPU interrupt status register</description>
|
||||
</register>
|
||||
<register name="LINK" type="CtrlReg" offset="0x0E22"
|
||||
size="2">
|
||||
<register name="LINK" type="CtrlReg" value="0x0E22" size="2">
|
||||
<description>???</description>
|
||||
</register>
|
||||
<register name="SGLR" type="CtrlReg" offset="0x0E24"
|
||||
size="2">
|
||||
<register name="SGLR" type="CtrlReg" value="0x0E24" size="2">
|
||||
<description>service grant latch register</description>
|
||||
</register>
|
||||
<register name="DCNR" type="CtrlReg" offset="0x0E26"
|
||||
size="2">
|
||||
<register name="DCNR" type="CtrlReg" value="0x0E26" size="2">
|
||||
<description>decoded channel number register</description>
|
||||
</register>
|
||||
|
||||
<!-- Port E Registers -->
|
||||
|
||||
<register name="PORTE0" type="CtrlReg" offset="0x0A11"
|
||||
<register name="PORTE0" type="CtrlReg" value="0x0A11"
|
||||
size="1">
|
||||
<description>Port E data register 0</description>
|
||||
</register>
|
||||
<register name="PORTE1" type="CtrlReg" offset="0x0A13"
|
||||
<register name="PORTE1" type="CtrlReg" value="0x0A13"
|
||||
size="1">
|
||||
<description>Port E data register 1</description>
|
||||
</register>
|
||||
<register name="DDRE" type="CtrlReg" offset="0x0A15"
|
||||
size="1">
|
||||
<register name="DDRE" type="CtrlReg" value="0x0A15" size="1">
|
||||
<description>Port E data direction register</description>
|
||||
</register>
|
||||
<register name="PEPAR" type="CtrlReg" offset="0x0A17"
|
||||
<register name="PEPAR" type="CtrlReg" value="0x0A17"
|
||||
size="1">
|
||||
<description>Port E pin assignment register</description>
|
||||
</register>
|
||||
|
||||
<!-- Port F Registers -->
|
||||
|
||||
<register name="PORTF0" type="CtrlReg" offset="0x0A19"
|
||||
<register name="PORTF0" type="CtrlReg" value="0x0A19"
|
||||
size="1">
|
||||
<description>Port F data register 0</description>
|
||||
</register>
|
||||
<register name="PORTF1" type="CtrlReg" offset="0x0A1B"
|
||||
<register name="PORTF1" type="CtrlReg" value="0x0A1B"
|
||||
size="1">
|
||||
<description>Port F data register 1</description>
|
||||
</register>
|
||||
<register name="DDRF" type="CtrlReg" offset="0x0A1D"
|
||||
size="1">
|
||||
<register name="DDRF" type="CtrlReg" value="0x0A1D" size="1">
|
||||
<description>Port F data direction register</description>
|
||||
</register>
|
||||
<register name="PFPAR" type="CtrlReg" offset="0x0A1F"
|
||||
<register name="PFPAR" type="CtrlReg" value="0x0A1F"
|
||||
size="1">
|
||||
<description>Port F pin assignment register</description>
|
||||
</register>
|
||||
|
||||
<!-- TPU parameter ram start addresses -->
|
||||
|
||||
<register name="CH0" type="CtrlReg" offset="0x0F00"
|
||||
size="2">
|
||||
<register name="CH0" type="CtrlReg" value="0x0F00" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH1" type="CtrlReg" offset="0x0F10"
|
||||
size="2">
|
||||
<register name="CH1" type="CtrlReg" value="0x0F10" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH2" type="CtrlReg" offset="0x0F20"
|
||||
size="2">
|
||||
<register name="CH2" type="CtrlReg" value="0x0F20" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH3" type="CtrlReg" offset="0x0F30"
|
||||
size="2">
|
||||
<register name="CH3" type="CtrlReg" value="0x0F30" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH4" type="CtrlReg" offset="0x0F40"
|
||||
size="2">
|
||||
<register name="CH4" type="CtrlReg" value="0x0F40" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH5" type="CtrlReg" offset="0x0F50"
|
||||
size="2">
|
||||
<register name="CH5" type="CtrlReg" value="0x0F50" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH6" type="CtrlReg" offset="0x0F60"
|
||||
size="2">
|
||||
<register name="CH6" type="CtrlReg" value="0x0F60" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH7" type="CtrlReg" offset="0x0F70"
|
||||
size="2">
|
||||
<register name="CH7" type="CtrlReg" value="0x0F70" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH8" type="CtrlReg" offset="0x0F80"
|
||||
size="2">
|
||||
<register name="CH8" type="CtrlReg" value="0x0F80" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH9" type="CtrlReg" offset="0x0F90"
|
||||
size="2">
|
||||
<register name="CH9" type="CtrlReg" value="0x0F90" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH10" type="CtrlReg" offset="0x0FA0"
|
||||
size="2">
|
||||
<register name="CH10" type="CtrlReg" value="0x0FA0" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH11" type="CtrlReg" offset="0x0FB0"
|
||||
size="2">
|
||||
<register name="CH11" type="CtrlReg" value="0x0FB0" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH12" type="CtrlReg" offset="0x0FC0"
|
||||
size="2">
|
||||
<register name="CH12" type="CtrlReg" value="0x0FC0" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH13" type="CtrlReg" offset="0x0FD0"
|
||||
size="2">
|
||||
<register name="CH13" type="CtrlReg" value="0x0FD0" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH14" type="CtrlReg" offset="0x0FE0"
|
||||
size="2">
|
||||
<register name="CH14" type="CtrlReg" value="0x0FE0" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
<register name="CH15" type="CtrlReg" offset="0x0FF0"
|
||||
size="2">
|
||||
<register name="CH15" type="CtrlReg" value="0x0FF0" size="2">
|
||||
<description>TPU parameter ram start address</description>
|
||||
</register>
|
||||
|
||||
<!-- queued serial module -->
|
||||
|
||||
<register name="QMCR" type="CtrlReg" offset="0x0C00"
|
||||
size="2">
|
||||
<register name="QMCR" type="CtrlReg" value="0x0C00" size="2">
|
||||
<description>QSM configuration register</description>
|
||||
</register>
|
||||
<register name="QTEST" type="CtrlReg" offset="0x0C02"
|
||||
<register name="QTEST" type="CtrlReg" value="0x0C02"
|
||||
size="2">
|
||||
<description>QSM test register</description>
|
||||
</register>
|
||||
<register name="QILR" type="CtrlReg" offset="0x0C04"
|
||||
size="1">
|
||||
<register name="QILR" type="CtrlReg" value="0x0C04" size="1">
|
||||
<description>QSM interrupt level register</description>
|
||||
</register>
|
||||
<register name="QIVR" type="CtrlReg" offset="0x0C05"
|
||||
size="1">
|
||||
<register name="QIVR" type="CtrlReg" value="0x0C05" size="1">
|
||||
<description>QSM interrupt vector register</description>
|
||||
</register>
|
||||
<register name="SCCR0" type="CtrlReg" offset="0x0C08"
|
||||
<register name="SCCR0" type="CtrlReg" value="0x0C08"
|
||||
size="2">
|
||||
<description>SCI control register 0</description>
|
||||
</register>
|
||||
<register name="SCCR1" type="CtrlReg" offset="0x0C0A"
|
||||
<register name="SCCR1" type="CtrlReg" value="0x0C0A"
|
||||
size="2">
|
||||
<description>SCI control register 1</description>
|
||||
</register>
|
||||
<register name="SCSR" type="CtrlReg" offset="0x0C0C"
|
||||
size="2">
|
||||
<register name="SCSR" type="CtrlReg" value="0x0C0C" size="2">
|
||||
<description>SCI status register</description>
|
||||
</register>
|
||||
<register name="SCDR" type="CtrlReg" offset="0x0C0E"
|
||||
size="2">
|
||||
<register name="SCDR" type="CtrlReg" value="0x0C0E" size="2">
|
||||
<description>SCI data register</description>
|
||||
</register>
|
||||
|
||||
<register name="QPDR" type="CtrlReg" offset="0x0C15"
|
||||
size="2">
|
||||
<register name="QPDR" type="CtrlReg" value="0x0C15" size="2">
|
||||
<description>QSM port data register</description>
|
||||
</register>
|
||||
<register name="QPAR" type="CtrlReg" offset="0x0C16"
|
||||
size="2">
|
||||
<register name="QPAR" type="CtrlReg" value="0x0C16" size="2">
|
||||
<description>QSM pin assignment register</description>
|
||||
</register>
|
||||
<register name="QDDR" type="CtrlReg" offset="0x0C17"
|
||||
size="2">
|
||||
<register name="QDDR" type="CtrlReg" value="0x0C17" size="2">
|
||||
<description>QSM data direction register</description>
|
||||
</register>
|
||||
<register name="SPCR0" type="CtrlReg" offset="0x0C18"
|
||||
<register name="SPCR0" type="CtrlReg" value="0x0C18"
|
||||
size="2">
|
||||
<description>QSPI control register 0</description>
|
||||
</register>
|
||||
<register name="SPCR1" type="CtrlReg" offset="0x0C1A"
|
||||
<register name="SPCR1" type="CtrlReg" value="0x0C1A"
|
||||
size="2">
|
||||
<description>QSPI control register 1</description>
|
||||
</register>
|
||||
<register name="SPCR2" type="CtrlReg" offset="0x0C1C"
|
||||
<register name="SPCR2" type="CtrlReg" value="0x0C1C"
|
||||
size="2">
|
||||
<description>QSPI control register 2</description>
|
||||
</register>
|
||||
<register name="SPCR3" type="CtrlReg" offset="0x0C1E"
|
||||
<register name="SPCR3" type="CtrlReg" value="0x0C1E"
|
||||
size="1">
|
||||
<description>QSPI control register 3</description>
|
||||
</register>
|
||||
<register name="SPSR" type="CtrlReg" offset="0x0C1F"
|
||||
size="1">
|
||||
<register name="SPSR" type="CtrlReg" value="0x0C1F" size="1">
|
||||
<description>QSPI status register</description>
|
||||
</register>
|
||||
|
||||
<register name="QRXD" type="CtrlReg" offset="0x0D00"
|
||||
size="2">
|
||||
<register name="QRXD" type="CtrlReg" value="0x0D00" size="2">
|
||||
<description>QSPI receive data</description>
|
||||
</register>
|
||||
<register name="QTXD" type="CtrlReg" offset="0x0D20"
|
||||
size="2">
|
||||
<register name="QTXD" type="CtrlReg" value="0x0D20" size="2">
|
||||
<description>QSPI transmit data</description>
|
||||
</register>
|
||||
<register name="QCMD" type="CtrlReg" offset="0x0D40"
|
||||
size="2">
|
||||
<register name="QCMD" type="CtrlReg" value="0x0D40" size="2">
|
||||
<description>QSPI command control</description>
|
||||
</register>
|
||||
</registerGroup>
|
||||
|
||||
17
mcdp/resources/targets/mpc555/registerDictionary.dtd
Normal file
17
mcdp/resources/targets/mpc555/registerDictionary.dtd
Normal file
@@ -0,0 +1,17 @@
|
||||
<?xml version='1.0' encoding='utf-8'?>
|
||||
|
||||
<!-- DTD for MPC555 RegisterDictionary.
|
||||
Only the type values are MPC555 specific.
|
||||
-->
|
||||
|
||||
<!ELEMENT registerDefinitions ((registerGroup*, register*) | (register*, registerGroup*))>
|
||||
<!ELEMENT registerGroup (register+)>
|
||||
<!ATTLIST registerGroup
|
||||
baseAddress CDATA #REQUIRED>
|
||||
<!ELEMENT register (description?)>
|
||||
<!ATTLIST register
|
||||
name CDATA #REQUIRED
|
||||
type (CtrlReg|GPR|FPR|SPR|MSR|CR|FPSCR) #REQUIRED
|
||||
value CDATA #REQUIRED
|
||||
size (1|2|4) #REQUIRED>
|
||||
<!ELEMENT description (#PCDATA)>
|
||||
370
mcdp/resources/targets/mpc555/registerDictionary.xml
Normal file
370
mcdp/resources/targets/mpc555/registerDictionary.xml
Normal file
@@ -0,0 +1,370 @@
|
||||
<?xml version='1.0' encoding='utf-8'?>
|
||||
|
||||
<!-- Register Definitions for the Motorola MC68332 Microcontroller -->
|
||||
<!DOCTYPE registerDefinitions SYSTEM "registerDictionary.dtd">
|
||||
|
||||
<registerDefinitions>
|
||||
<register name="R0" type="GPR" value="0" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R1" type="GPR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R2" type="GPR" value="2" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R3" type="GPR" value="3" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R4" type="GPR" value="4" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R5" type="GPR" value="5" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R6" type="GPR" value="6" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R7" type="GPR" value="7" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R8" type="GPR" value="8" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R9" type="GPR" value="9" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R10" type="GPR" value="10" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R11" type="GPR" value="11" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R12" type="GPR" value="12" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R13" type="GPR" value="13" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R14" type="GPR" value="14" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R15" type="GPR" value="15" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R16" type="GPR" value="16" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R17" type="GPR" value="17" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R18" type="GPR" value="18" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R19" type="GPR" value="19" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R20" type="GPR" value="20" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R21" type="GPR" value="21" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R22" type="GPR" value="22" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R23" type="GPR" value="23" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R24" type="GPR" value="24" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R25" type="GPR" value="25" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R26" type="GPR" value="26" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R27" type="GPR" value="27" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R28" type="GPR" value="28" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R29" type="GPR" value="29" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R30" type="GPR" value="30" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="R31" type="GPR" value="31" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR0" type="FPR" value="0" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR1" type="FPR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR2" type="FPR" value="2" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR3" type="FPR" value="3" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR4" type="FPR" value="4" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR5" type="FPR" value="5" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR6" type="FPR" value="6" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR7" type="FPR" value="7" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR8" type="FPR" value="8" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR9" type="FPR" value="9" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR10" type="FPR" value="10" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR11" type="FPR" value="11" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR12" type="FPR" value="12" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR13" type="FPR" value="13" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR14" type="FPR" value="14" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR15" type="FPR" value="15" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR16" type="FPR" value="16" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR17" type="FPR" value="17" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR18" type="FPR" value="18" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR19" type="FPR" value="19" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR20" type="FPR" value="20" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR21" type="FPR" value="21" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR22" type="FPR" value="22" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR23" type="FPR" value="23" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR24" type="FPR" value="24" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR25" type="FPR" value="25" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR26" type="FPR" value="26" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR27" type="FPR" value="27" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR28" type="FPR" value="28" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR29" type="FPR" value="29" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR30" type="FPR" value="30" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPR31" type="FPR" value="31" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR1" type="SPR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="XER" type="SPR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR8" type="SPR" value="8" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="LR" type="SPR" value="8" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR9" type="SPR" value="9" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="CTR" type="SPR" value="9" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR18" type="SPR" value="18" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="DSISR" type="SPR" value="18" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR19" type="SPR" value="19" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="DAR" type="SPR" value="19" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR22" type="SPR" value="22" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="DEC" type="SPR" value="22" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR26" type="SPR" value="26" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SRR0" type="SPR" value="26" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR27" type="SPR" value="27" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SRR1" type="SPR" value="27" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR148" type="SPR" value="148" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="ECR" type="SPR" value="148" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR149" type="SPR" value="149" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="DER" type="SPR" value="149" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR156" type="SPR" value="156" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="LCTRL1" type="SPR" value="156" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR157" type="SPR" value="157" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="LCTRL2" type="SPR" value="157" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR158" type="SPR" value="158" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="ICTRL" type="SPR" value="158" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR268" type="SPR" value="268" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="TBL" type="SPR" value="268" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR269" type="SPR" value="269" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="TBU" type="SPR" value="269" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR272" type="SPR" value="272" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPRG0" type="SPR" value="272" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR273" type="SPR" value="273" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPRG1" type="SPR" value="273" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR274" type="SPR" value="274" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPRG2" type="SPR" value="274" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR275" type="SPR" value="275" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPRG3" type="SPR" value="275" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR284" type="SPR" value="284" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="TBL" type="SPR" value="284" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR285" type="SPR" value="285" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="TBU" type="SPR" value="285" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR287" type="SPR" value="287" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="PVR" type="SPR" value="287" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SPR638" type="SPR" value="638" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="IMMR" type="SPR" value="638" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="MSR" type="MSR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="CR" type="CR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="FPSCR" type="FPSCR" value="1" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="BR0" type="CtrlReg" value="0x2FC100" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="OR0" type="CtrlReg" value="0x2FC104" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="BR1" type="CtrlReg" value="0x2FC108" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="OR1" type="CtrlReg" value="0x2FC10C" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="DMBR" type="CtrlReg" value="0x2FC140" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="DMOR" type="CtrlReg" value="0x2FC144" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="RSR" type="CtrlReg" value="0x2FC288" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
<register name="SYPCR" type="CtrlReg" value="0x2FC004" size="4">
|
||||
<description></description>
|
||||
</register>
|
||||
</registerDefinitions>
|
||||
Reference in New Issue
Block a user