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8708aa2e0eb16a0387d72f8b702171e654abf73e
jlibusb/mcdp/resources/targets/mpc555/registerDictionary.xml
schlaepfer 8708aa2e0e - register element attributes added/changed: 
* name -> mnemonic
* altmnemonic
* accessmode
* accessattr
- register dict updated
- Register class redesigned

git-svn-id: https://svn.code.sf.net/p/libusbjava/code/trunk@114 94ad28fe-ef68-46b1-9651-e7ae4fcf1c4c
2006-03-16 07:47:05 +00:00

1955 lines
71 KiB
XML
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<?xml version='1.0' encoding='utf-8'?>
<!-- Register Definitions for the Motorola MPC555 Microcontroller -->
<!DOCTYPE registerDefinitions SYSTEM "registerDictionary.dtd">
<registerDefinitions>
<!-- General Purpose Registers -->
<register mnemonic="GPR0" altmnemonic="R0" type="GPR" value="0"
size="4">
<description>General Purpose Register 0</description>
</register>
<register mnemonic="GPR1" altmnemonic="R1" type="GPR" value="1"
size="4">
<description>General Purpose Register 1</description>
</register>
<register mnemonic="GPR2" altmnemonic="R2" type="GPR" value="2"
size="4">
<description>General Purpose Register 2</description>
</register>
<register mnemonic="GPR3" altmnemonic="R3" type="GPR" value="3"
size="4">
<description>General Purpose Register 3</description>
</register>
<register mnemonic="GPR4" altmnemonic="R4" type="GPR" value="4"
size="4">
<description>General Purpose Register 4</description>
</register>
<register mnemonic="GPR5" altmnemonic="R5" type="GPR" value="5"
size="4">
<description>General Purpose Register 5</description>
</register>
<register mnemonic="GPR6" altmnemonic="R6" type="GPR" value="6"
size="4">
<description>General Purpose Register 6</description>
</register>
<register mnemonic="GPR7" altmnemonic="R7" type="GPR" value="7"
size="4">
<description>General Purpose Register 7</description>
</register>
<register mnemonic="GPR8" altmnemonic="R8" type="GPR" value="8"
size="4">
<description>General Purpose Register 8</description>
</register>
<register mnemonic="GPR9" altmnemonic="R9" type="GPR" value="9"
size="4">
<description>General Purpose Register 9</description>
</register>
<register mnemonic="GPR10" altmnemonic="R10" type="GPR" value="10"
size="4">
<description>General Purpose Register 10</description>
</register>
<register mnemonic="GPR11" altmnemonic="R11" type="GPR" value="11"
size="4">
<description>General Purpose Register 11</description>
</register>
<register mnemonic="GPR12" altmnemonic="R12" type="GPR" value="12"
size="4">
<description>General Purpose Register 12</description>
</register>
<register mnemonic="GPR13" altmnemonic="R13" type="GPR" value="13"
size="4">
<description>General Purpose Register 13</description>
</register>
<register mnemonic="GPR14" altmnemonic="R14" type="GPR" value="14"
size="4">
<description>General Purpose Register 14</description>
</register>
<register mnemonic="GPR15" altmnemonic="R15" type="GPR" value="15"
size="4">
<description>General Purpose Register 15</description>
</register>
<register mnemonic="GPR16" altmnemonic="R16" type="GPR" value="16"
size="4">
<description>General Purpose Register 16</description>
</register>
<register mnemonic="GPR17" altmnemonic="R17" type="GPR" value="17"
size="4">
<description>General Purpose Register 17</description>
</register>
<register mnemonic="GPR18" altmnemonic="R18" type="GPR" value="18"
size="4">
<description>General Purpose Register 18</description>
</register>
<register mnemonic="GPR19" altmnemonic="R19" type="GPR" value="19"
size="4">
<description>General Purpose Register 19</description>
</register>
<register mnemonic="GPR20" altmnemonic="R20" type="GPR" value="20"
size="4">
<description>General Purpose Register 20</description>
</register>
<register mnemonic="GPR21" altmnemonic="R21" type="GPR" value="21"
size="4">
<description>General Purpose Register 21</description>
</register>
<register mnemonic="GPR22" altmnemonic="R22" type="GPR" value="22"
size="4">
<description>General Purpose Register 22</description>
</register>
<register mnemonic="GPR23" altmnemonic="R23" type="GPR" value="23"
size="4">
<description>General Purpose Register 23</description>
</register>
<register mnemonic="GPR24" altmnemonic="R24" type="GPR" value="24"
size="4">
<description>General Purpose Register 24</description>
</register>
<register mnemonic="GPR25" altmnemonic="R25" type="GPR" value="25"
size="4">
<description>General Purpose Register 25</description>
</register>
<register mnemonic="GPR26" altmnemonic="R26" type="GPR" value="26"
size="4">
<description>General Purpose Register 26</description>
</register>
<register mnemonic="GPR27" altmnemonic="R27" type="GPR" value="27"
size="4">
<description>General Purpose Register 27</description>
</register>
<register mnemonic="GPR28" altmnemonic="R28" type="GPR" value="28"
size="4">
<description>General Purpose Register 28</description>
</register>
<register mnemonic="GPR29" altmnemonic="R29" type="GPR" value="29"
size="4">
<description>General Purpose Register 29</description>
</register>
<register mnemonic="GPR30" altmnemonic="R30" type="GPR" value="30"
size="4">
<description>General Purpose Register 30</description>
</register>
<register mnemonic="GPR31" altmnemonic="R31" type="GPR" value="31"
size="4">
<description>General Purpose Register 31</description>
</register>
<!-- Floating-Point Registers -->
<register mnemonic="FPR0" type="FPR" value="0" size="4">
<description>Floating-Point Register 0</description>
</register>
<register mnemonic="FPR1" type="FPR" value="1" size="4">
<description>Floating-Point Register 1</description>
</register>
<register mnemonic="FPR2" type="FPR" value="2" size="4">
<description>Floating-Point Register 2</description>
</register>
<register mnemonic="FPR3" type="FPR" value="3" size="4">
<description>Floating-Point Register 3</description>
</register>
<register mnemonic="FPR4" type="FPR" value="4" size="4">
<description>Floating-Point Register 4</description>
</register>
<register mnemonic="FPR5" type="FPR" value="5" size="4">
<description>Floating-Point Register 5</description>
</register>
<register mnemonic="FPR6" type="FPR" value="6" size="4">
<description>Floating-Point Register 6</description>
</register>
<register mnemonic="FPR7" type="FPR" value="7" size="4">
<description>Floating-Point Register 7</description>
</register>
<register mnemonic="FPR8" type="FPR" value="8" size="4">
<description>Floating-Point Register 8</description>
</register>
<register mnemonic="FPR9" type="FPR" value="9" size="4">
<description>Floating-Point Register 9</description>
</register>
<register mnemonic="FPR10" type="FPR" value="10" size="4">
<description>Floating-Point Register 10</description>
</register>
<register mnemonic="FPR11" type="FPR" value="11" size="4">
<description>Floating-Point Register 11</description>
</register>
<register mnemonic="FPR12" type="FPR" value="12" size="4">
<description>Floating-Point Register 12</description>
</register>
<register mnemonic="FPR13" type="FPR" value="13" size="4">
<description>Floating-Point Register 13</description>
</register>
<register mnemonic="FPR14" type="FPR" value="14" size="4">
<description>Floating-Point Register 14</description>
</register>
<register mnemonic="FPR15" type="FPR" value="15" size="4">
<description>Floating-Point Register 15</description>
</register>
<register mnemonic="FPR16" type="FPR" value="16" size="4">
<description>Floating-Point Register 16</description>
</register>
<register mnemonic="FPR17" type="FPR" value="17" size="4">
<description>Floating-Point Register 17</description>
</register>
<register mnemonic="FPR18" type="FPR" value="18" size="4">
<description>Floating-Point Register 18</description>
</register>
<register mnemonic="FPR19" type="FPR" value="19" size="4">
<description>Floating-Point Register 19</description>
</register>
<register mnemonic="FPR20" type="FPR" value="20" size="4">
<description>Floating-Point Register 20</description>
</register>
<register mnemonic="FPR21" type="FPR" value="21" size="4">
<description>Floating-Point Register 21</description>
</register>
<register mnemonic="FPR22" type="FPR" value="22" size="4">
<description>Floating-Point Register 22</description>
</register>
<register mnemonic="FPR23" type="FPR" value="23" size="4">
<description>Floating-Point Register 23</description>
</register>
<register mnemonic="FPR24" type="FPR" value="24" size="4">
<description>Floating-Point Register 24</description>
</register>
<register mnemonic="FPR25" type="FPR" value="25" size="4">
<description>Floating-Point Register 25</description>
</register>
<register mnemonic="FPR26" type="FPR" value="26" size="4">
<description>Floating-Point Register 26</description>
</register>
<register mnemonic="FPR27" type="FPR" value="27" size="4">
<description>Floating-Point Register 27</description>
</register>
<register mnemonic="FPR28" type="FPR" value="28" size="4">
<description>Floating-Point Register 28</description>
</register>
<register mnemonic="FPR29" type="FPR" value="29" size="4">
<description>Floating-Point Register 29</description>
</register>
<register mnemonic="FPR30" type="FPR" value="30" size="4">
<description>Floating-Point Register 30</description>
</register>
<register mnemonic="FPR31" type="FPR" value="31" size="4">
<description>Floating-Point Register 31</description>
</register>
<!-- SPRs -->
<register mnemonic="SPR1" altmnemonic="XER" type="SPR" value="1"
size="4" accessmode="user">
<description>Integer Exception Register (XER)</description>
</register>
<register mnemonic="SPR8" altmnemonic="LR" type="SPR" value="8"
size="4" accessmode="user">
<description>Link Register (LR)</description>
</register>
<register mnemonic="SPR9" altmnemonic="CTR" type="SPR" value="9"
size="4" accessmode="user">
<description>Count Register (CTR)</description>
</register>
<register mnemonic="SPR18" altmnemonic="DSISR" type="SPR" value="18"
size="4" accessmode="supervisor">
<description>
DAE/ Source Instruction Service Register (DSISR)
</description>
</register>
<register mnemonic="SPR19" altmnemonic="DAR" type="SPR" value="19"
size="4" accessmode="supervisor">
<description>Data Address Register (DAR)</description>
</register>
<register mnemonic="SPR22" altmnemonic="DEC" type="SPR" value="22"
size="4" accessmode="supervisor">
<description>Decrement Register (DEC)</description>
</register>
<register mnemonic="SPR26" altmnemonic="SRR0" type="SPR" value="26"
size="4" accessmode="supervisor">
<description>Save and Restore Register 0 (SRR0)</description>
</register>
<register mnemonic="SPR27" altmnemonic="SRR1" type="SPR" value="27"
size="4" accessmode="supervisor">
<description>Save and Restore Register 1 (SRR1)</description>
</register>
<register mnemonic="SPR80" altmnemonic="EIE" type="SPR" value="80"
size="4" accessmode="supervisor">
<description>External Interrupt Enable (EIE)</description>
</register>
<register mnemonic="SPR81" altmnemonic="EID" type="SPR" value="81"
size="4" accessmode="supervisor">
<description>External Interrupt Disable (EID)</description>
</register>
<register mnemonic="SPR82" altmnemonic="NRI" type="SPR" value="82"
size="4" accessmode="supervisor">
<description>Non-Recoverable Interrupt (NRI)</description>
</register>
<register mnemonic="SPR144" altmnemonic="CMPA" type="SPR"
value="144" size="4" accessmode="supervisor">
<description>Comparator A Value Register (CMPA)</description>
</register>
<register mnemonic="SPR145" altmnemonic="CMPB" type="SPR"
value="145" size="4" accessmode="supervisor">
<description>Comparator B Value Register (CMPB)</description>
</register>
<register mnemonic="SPR146" altmnemonic="CMPC" type="SPR"
value="146" size="4" accessmode="supervisor">
<description>Comparator C Value Register (CMPC)</description>
</register>
<register mnemonic="SPR147" altmnemonic="CMPD" type="SPR"
value="147" size="4" accessmode="supervisor">
<description>Comparator D Value Register (CMPD)</description>
</register>
<register mnemonic="SPR148" altmnemonic="ECR" type="SPR" value="148"
size="4" accessmode="supervisor">
<description>Exception Cause Register (ECR)</description>
</register>
<register mnemonic="SPR149" altmnemonic="DER" type="SPR" value="149"
size="4" accessmode="supervisor">
<description>Debug Enable Register (DER)</description>
</register>
<register mnemonic="SPR150" altmnemonic="COUNTA" type="SPR"
value="150" size="4" accessmode="supervisor">
<description>
Breakpoint Counter A Value and Control (COUNTA)
</description>
</register>
<register mnemonic="SPR151" altmnemonic="COUNTB" type="SPR"
value="151" size="4" accessmode="supervisor">
<description>
Breakpoint Counter B Value and Control (COUNTB)
</description>
</register>
<register mnemonic="SPR152" altmnemonic="CMPE" type="SPR"
value="152" size="4" accessmode="supervisor">
<description>Comparator E Value Register (CMPE)</description>
</register>
<register mnemonic="SPR153" altmnemonic="CMPF" type="SPR"
value="153" size="4" accessmode="supervisor">
<description>Comparator F Value Register (CMPF)</description>
</register>
<register mnemonic="SPR154" altmnemonic="CMPG" type="SPR"
value="154" size="4" accessmode="supervisor">
<description>Comparator G Value Register (CMPG)</description>
</register>
<register mnemonic="SPR155" altmnemonic="CMPH" type="SPR"
value="155" size="4" accessmode="supervisor">
<description>Comparator H Value Register (CMPH)</description>
</register>
<register mnemonic="SPR156" altmnemonic="LCTRL1" type="SPR"
value="156" size="4" accessmode="supervisor">
<description>
L-Bus Support Comparators Control (LCTRL1)
</description>
</register>
<register mnemonic="SPR157" altmnemonic="LCTRL2" type="SPR"
value="157" size="4" accessmode="supervisor">
<description>
L-Bus Support Comparators Control (LCTRL2)
</description>
</register>
<register mnemonic="SPR158" altmnemonic="ICTRL" type="SPR"
value="158" size="4" accessmode="supervisor">
<description>
I-Bus Support Control Register (ICTRL)
</description>
</register>
<register mnemonic="SPR159" altmnemonic="BAR" type="SPR" value="159"
size="4" accessmode="supervisor">
<description>Breakpoint Address Register (BAR)</description>
</register>
<register mnemonic="SPR268" altmnemonic="TBLR" type="SPR"
value="268" size="4" accessmode="user" accessattr="readonly">
<description>Time Base Lower - Read (TBLR)</description>
</register>
<register mnemonic="SPR269" altmnemonic="TBUR" type="SPR"
value="269" size="4" accessmode="user" accessattr="readonly">
<description>Time Base Upper - Read (TBUR)</description>
</register>
<register mnemonic="SPR272" altmnemonic="SPRG0" type="SPR"
value="272" size="4" accessmode="supervisor">
<description>SPR General 0 (SPRG0)</description>
</register>
<register mnemonic="SPR273" altmnemonic="SPRG1" type="SPR"
value="273" size="4" accessmode="supervisor">
<description>SPR General 1 (SPRG1)</description>
</register>
<register mnemonic="SPR274" altmnemonic="SPRG2" type="SPR"
value="274" size="4" accessmode="supervisor">
<description>SPR General 2 (SPRG2)</description>
</register>
<register mnemonic="SPR275" altmnemonic="SPRG3" type="SPR"
value="275" size="4" accessmode="supervisor">
<description>SPR General 3 (SPRG3)</description>
</register>
<register mnemonic="SPR284" altmnemonic="TBLW" type="SPR"
value="284" size="4" accessmode="supervisor" accessattr="writeonly">
<description>Time Base Lower - Write (TBLW)</description>
</register>
<register mnemonic="SPR285" altmnemonic="TBUW" type="SPR"
value="285" size="4" accessmode="supervisor" accessattr="writeonly">
<description>Time Base Upper - Write (TBUW)</description>
</register>
<register mnemonic="SPR287" altmnemonic="PVR" type="SPR" value="287"
size="4" accessmode="supervisor" accessattr="readonly">
<description>Processor Version Register (PVR)</description>
</register>
<register mnemonic="SPR528" altmnemonic="MI_GRA" type="SPR"
value="528" size="4" accessmode="supervisor">
<description>
Global Region Attribute Register (MI_GRA)
</description>
</register>
<register mnemonic="SPR536" altmnemonic="L2U_GRA" type="SPR"
value="536" size="4" accessmode="supervisor">
<description>
L2U Global Region Attribute Register (L2U_GRA)
</description>
</register>
<register mnemonic="SPR560" altmnemonic="BBCMCR" type="SPR"
value="560" size="4" accessmode="supervisor">
<description>
BBC Module Configuration Register (BBCMCR)
</description>
</register>
<register mnemonic="SPR568" altmnemonic="L2U_MCR" type="SPR"
value="568" size="4" accessmode="user">
<description>
L2U Module Configuration Register (L2U_MCR)
</description>
</register>
<register mnemonic="SPR630" altmnemonic="DPDR" type="SPR"
value="630" size="4" accessmode="supervisor">
<description>Development Port Data Register (DPDR)</description>
</register>
<register mnemonic="SPR638" altmnemonic="IMMR" type="SPR"
value="638" size="4" accessmode="supervisor">
<description>Internal Memory Map Register (IMMR)</description>
</register>
<register mnemonic="SPR784" altmnemonic="MI_RBA0" type="SPR"
value="784" size="4" accessmode="supervisor">
<description>Region Address Register 0 (MI_RBA0)</description>
</register>
<register mnemonic="SPR785" altmnemonic="MI_RBA1" type="SPR"
value="785" size="4" accessmode="supervisor">
<description>Region Address Register 1 (MI_RBA1)</description>
</register>
<register mnemonic="SPR786" altmnemonic="MI_RBA2" type="SPR"
value="786" size="4" accessmode="supervisor">
<description>Region Address Register 2 (MI_RBA2)</description>
</register>
<register mnemonic="SPR787" altmnemonic="MI_RBA3" type="SPR"
value="787" size="4" accessmode="supervisor">
<description>Region Address Register 3 (MI_RBA3)</description>
</register>
<register mnemonic="SPR792" altmnemonic="L2U_RBA0" type="SPR"
value="792" size="4" accessmode="supervisor">
<description>
L2U Region 0 Address Register (L2U_RBA0)
</description>
</register>
<register mnemonic="SPR793" altmnemonic="L2U_RBA1" type="SPR"
value="793" size="4" accessmode="supervisor">
<description>
L2U Region 1 Address Register (L2U_RBA1)
</description>
</register>
<register mnemonic="SPR794" altmnemonic="L2U_RBA2" type="SPR"
value="794" size="4" accessmode="supervisor">
<description>
L2U Region 2 Address Register (L2U_RBA2)
</description>
</register>
<register mnemonic="SPR795" altmnemonic="L2U_RBA3" type="SPR"
value="795" size="4" accessmode="supervisor">
<description>
L2U Region 3Address Register (L2U_RBA3)
</description>
</register>
<register mnemonic="SPR816" altmnemonic="MI_RA0" type="SPR"
value="816" size="4" accessmode="supervisor">
<description>Region Attribute Register 0 (MI_RA0)</description>
</register>
<register mnemonic="SPR817" altmnemonic="MI_RA1" type="SPR"
value="817" size="4" accessmode="supervisor">
<description>Region Attribute Register 1 (MI_RA1)</description>
</register>
<register mnemonic="SPR818" altmnemonic="MI_RA2" type="SPR"
value="818" size="4" accessmode="supervisor">
<description>Region Attribute Register 2 (MI_RA2)</description>
</register>
<register mnemonic="SPR819" altmnemonic="MI_RA3" type="SPR"
value="819" size="4" accessmode="supervisor">
<description>Region Attribute Register 3 (MI_RA3)</description>
</register>
<register mnemonic="SPR824" altmnemonic="L2U_RA0" type="SPR"
value="824" size="4" accessmode="supervisor">
<description>
L2U Region 0 Attribute Register (L2U_RA0)
</description>
</register>
<register mnemonic="SPR825" altmnemonic="L2U_RA1" type="SPR"
value="825" size="4" accessmode="supervisor">
<description>
L2U Region 1 Attribute Register (L2U_RA1)
</description>
</register>
<register mnemonic="SPR826" altmnemonic="L2U_RA2" type="SPR"
value="826" size="4" accessmode="supervisor">
<description>
L2U Region 2 Attribute Register (L2U_RA2)
</description>
</register>
<register mnemonic="SPR827" altmnemonic="L2U_RA3" type="SPR"
value="827" size="4" accessmode="supervisor">
<description>
L2U Region 3 Attribute Register (L2U_RA3)
</description>
</register>
<register mnemonic="SPR1022" altmnemonic="FPECR" type="SPR"
value="1022" size="4" accessmode="supervisor">
<description>
Floating-Point Exception Cause Register (FPECR)
</description>
</register>
<!-- Various Registers -->
<register mnemonic="MSR" type="MSR" value="1" size="4"
accessmode="supervisor">
<description>Machine State Register</description>
</register>
<register mnemonic="CR" type="CR" value="1" size="4">
<description>Count Register</description>
</register>
<register mnemonic="FPSCR" type="FPSCR" value="1" size="4">
<description>
Floating-Point Status and Control Register
</description>
</register>
<registerGroup baseAddress="0x2FC000">
<!-- Unified System Interface Unit (USIU) -->
<register mnemonic="SIUMCR" type="CtrlReg" value="0x000"
size="4" accessmode="user">
<description>SIU Module Configuration Register</description>
</register>
<register mnemonic="SYPCR" type="CtrlReg" value="0x004" size="4"
accessmode="user">
<description>
System Protection Control Register
</description>
</register>
<register mnemonic="SWSR" type="CtrlReg" value="0x00e" size="2"
accessmode="user" accessattr="writeonly">
<description>Software Service Register</description>
</register>
<register mnemonic="SIPEND" type="CtrlReg" value="0x010"
size="4" accessmode="user">
<description>Interrupt Pending Register</description>
</register>
<register mnemonic="SIMASK" type="CtrlReg" value="0x014"
size="4" accessmode="user">
<description>Interrupt Mask Register</description>
</register>
<register mnemonic="SIEL" type="CtrlReg" value="0x018" size="4"
accessmode="user">
<description>Interrupt Edge Level Mask</description>
</register>
<register mnemonic="SIVEC" type="CtrlReg" value="0x01c" size="4"
accessmode="user" accessattr="readonly">
<description>Interrupt Vector</description>
</register>
<register mnemonic="TESR" type="CtrlReg" value="0x020" size="4"
accessmode="user">
<description>Transfer Error Status Register</description>
</register>
<register mnemonic="SGPIODT1" type="CtrlReg" value="0x024"
size="4" accessmode="user">
<description>
USIU General-Purpose I/O Data Register 1
</description>
</register>
<register mnemonic="SGPIODT2" type="CtrlReg" value="0x028"
size="4" accessmode="user">
<description>
USIU General-Purpose I/O Data Register 2
</description>
</register>
<register mnemonic="SGPIOCR" type="CtrlReg" value="0x02c"
size="4" accessmode="user">
<description>
USIU General-Purpose I/O Control Register
</description>
</register>
<register mnemonic="EMCR" type="CtrlReg" value="0x030" size="4"
accessmode="user">
<description>
External Master Mode Control Register
</description>
</register>
<register mnemonic="PDMCR" type="CtrlReg" value="0x03c" size="4"
accessmode="user">
<description>
Pads Module Configuration Register
</description>
</register>
<!-- Memory Controller Registers -->
<register mnemonic="BR0" type="CtrlReg" value="0x100" size="4"
accessmode="user">
<description>Memory Control Base Register 0</description>
</register>
<register mnemonic="OR0" type="CtrlReg" value="0x104" size="4"
accessmode="user">
<description>Memory Control Option Register 0</description>
</register>
<register mnemonic="BR1" type="CtrlReg" value="0x108" size="4"
accessmode="user">
<description>Memory Control Base Register 1</description>
</register>
<register mnemonic="OR1" type="CtrlReg" value="0x10C" size="4"
accessmode="user">
<description>Memory Control Option Register 1</description>
</register>
<register mnemonic="BR2" type="CtrlReg" value="0x110" size="4"
accessmode="user">
<description>Memory Control Base Register 2</description>
</register>
<register mnemonic="OR2" type="CtrlReg" value="0x114" size="4"
accessmode="user">
<description>Memory Control Option Register 2</description>
</register>
<register mnemonic="BR3" type="CtrlReg" value="0x118" size="4"
accessmode="user">
<description>Memory Control Base Register 3</description>
</register>
<register mnemonic="OR3" type="CtrlReg" value="0x11C" size="4"
accessmode="user">
<description>Memory Control Option Register 3</description>
</register>
<register mnemonic="DMBR" type="CtrlReg" value="0x140" size="4"
accessmode="user">
<description>Dual Mapping Base Register</description>
</register>
<register mnemonic="DMOR" type="CtrlReg" value="0x144" size="4"
accessmode="user">
<description>Dual Mapping Option Register</description>
</register>
<register mnemonic="MSTAT" type="CtrlReg" value="0x178" size="4"
accessmode="user">
<description>Memory Status</description>
</register>
<!-- System Integration Timers -->
<register mnemonic="TBSCR" type="CtrlReg" value="0x200" size="4"
accessmode="user">
<description>Time Base Status and Control</description>
</register>
<register mnemonic="TBREF0" type="CtrlReg" value="0x204"
size="4" accessmode="user">
<description>Time Base Reference 0</description>
</register>
<register mnemonic="TBREF1" type="CtrlReg" value="0x208"
size="4" accessmode="user">
<description>Time Base Reference 1</description>
</register>
<register mnemonic="RTCSC" type="CtrlReg" value="0x220" size="4"
accessmode="user">
<description>
Real Time Clock Status and Control
</description>
</register>
<register mnemonic="RTC" type="CtrlReg" value="0x224" size="4"
accessmode="user">
<description>Real Time Clock</description>
</register>
<register mnemonic="RTSEC" type="CtrlReg" value="0x228" size="4"
accessmode="test">
<description>Real Time Alarm Seconds</description>
</register>
<register mnemonic="RTCAL" type="CtrlReg" value="0x22c" size="4"
accessmode="user">
<description>Real Time Alarm</description>
</register>
<register mnemonic="PISCR" type="CtrlReg" value="0x240" size="4"
accessmode="user">
<description>PIT Status and Control</description>
</register>
<register mnemonic="PITC" type="CtrlReg" value="0x224" size="4"
accessmode="user">
<description>PIT Count</description>
</register>
<register mnemonic="PITR" type="CtrlReg" value="0x248" size="4"
accessmode="user" accessattr="readonly">
<description>PIT Register</description>
</register>
<!-- Clocks and Reset -->
<register mnemonic="SCCR" type="CtrlReg" value="0x280" size="4"
accessmode="user">
<description>System Clock Control Register</description>
</register>
<register mnemonic="PLPRCR" type="CtrlReg" value="0x284"
size="4" accessmode="user">
<description>
PLL Low Power and Reset Control Register
</description>
</register>
<register mnemonic="RSR" type="CtrlReg" value="0x288" size="4"
accessmode="user">
<description>Reset Status Register</description>
</register>
<register mnemonic="COLIR" type="CtrlReg" value="0x28c" size="4"
accessmode="user">
<description>Change of Lock Interrupt Register</description>
</register>
<register mnemonic="VSRMCR" type="CtrlReg" value="0x290"
size="4" accessmode="user">
<description>VDDSRM Control Register</description>
</register>
<!-- System Integration Timer Keys -->
<register mnemonic="TBSCRK" type="CtrlReg" value="0x300"
size="4" accessmode="user">
<description>Time Base Status and Control Key</description>
</register>
<register mnemonic="TBREF0K" type="CtrlReg" value="0x304"
size="4" accessmode="user">
<description>Time Base Reference 0 Key</description>
</register>
<register mnemonic="TBREF1K" type="CtrlReg" value="0x308"
size="4" accessmode="user">
<description>Time Base Reference 1 Key</description>
</register>
<register mnemonic="TBK" type="CtrlReg" value="0x30c" size="4"
accessmode="user">
<description>Time Base and Decrementer Key</description>
</register>
<register mnemonic="RTCSCK" type="CtrlReg" value="0x320"
size="4" accessmode="user">
<description>
Real-Time Clock Status and Control Key
</description>
</register>
<register mnemonic="RTCK" type="CtrlReg" value="0x324" size="4"
accessmode="user">
<description>Real-Time Clock Key</description>
</register>
<register mnemonic="RTSECK" type="CtrlReg" value="0x328"
size="4" accessmode="user">
<description>Real-Time Alarm Seconds Key</description>
</register>
<register mnemonic="RTCALK" type="CtrlReg" value="0x32c"
size="4" accessmode="user">
<description>Real-Time Alarm Key</description>
</register>
<register mnemonic="PISCRIK" type="CtrlReg" value="0x340"
size="4" accessmode="user">
<description>PIT Status and Control Key</description>
</register>
<register mnemonic="PITCK" type="CtrlReg" value="0x344" size="4"
accessmode="user">
<description>PIT Count Key</description>
</register>
<!-- System Integration Timer Keys -->
<register mnemonic="SCCRK" type="CtrlReg" value="0x380" size="4"
accessmode="user">
<description>System Clock Control Key</description>
</register>
<register mnemonic="PLPRCRK" type="CtrlReg" value="0x384"
size="4" accessmode="user">
<description>
PLL Low-Power and Reset Control Register Key
</description>
</register>
<register mnemonic="RSRK" type="CtrlReg" value="0x388" size="4"
accessmode="user">
<description>Reset Status Register Key</description>
</register>
<!-- CMF (CDR MoneT Flash EEPROM) -->
<!-- CMF_A -->
<register mnemonic="CMFMCR" type="CtrlReg" value="0x800"
size="4" accessmode="supervisor">
<description>
CMF_A EEPROM Configuration Register
</description>
</register>
<register mnemonic="CMFTST" type="CtrlReg" value="0x804"
size="4" accessmode="supervisor">
<description>CMF_A EEPROM Test Register</description>
</register>
<register mnemonic="CMFCTL" type="CtrlReg" value="0x808"
size="4" accessmode="supervisor">
<description>
CMF_A EEPROM High Voltage Control Register
</description>
</register>
<!-- CMF_B -->
<register mnemonic="CMFMCR" type="CtrlReg" value="0x840"
size="4" accessmode="supervisor">
<description>
CMF_B EEPROM Configuration Register
</description>
</register>
<register mnemonic="CMFTST" type="CtrlReg" value="0x844"
size="4" accessmode="supervisor">
<description>CMF_B EEPROM Test Register</description>
</register>
<register mnemonic="CMFCTL" type="CtrlReg" value="0x848"
size="4" accessmode="supervisor">
<description>
CMF_B EEPROM High Voltage Control Register
</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x300000">
<!-- DPTRAM (Dual-Port TPU RAM) -->
<register mnemonic="DPTMCR" type="CtrlReg" value="0x000"
size="2" accessmode="supervisor">
<description>DPT Module Configuration Register</description>
</register>
<register mnemonic="RAMTST" type="CtrlReg" value="0x002"
size="2" accessmode="test">
<description>Test register, factory test only</description>
</register>
<register mnemonic="RAMBAR" type="CtrlReg" value="0x004"
size="2" accessmode="supervisor">
<description>RAM Array Address Register</description>
</register>
<register mnemonic="MISRH" type="CtrlReg" value="0x006" size="2"
accessmode="supervisor" accessattr="readonly">
<description>
Multiple Input Signature Register High
</description>
</register>
<register mnemonic="MISRL" type="CtrlReg" value="0x008" size="2"
accessmode="supervisor" accessattr="readonly">
<description>
Multiple Input Signature Register Low
</description>
</register>
<register mnemonic="MISCNT" type="CtrlReg" value="0x00a"
size="2" accessmode="supervisor" accessattr="readonly">
<description>MISC Counter</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x304000">
<!-- TPU3 (Time Processor Unit) -->
<!-- TPU_A -->
<register mnemonic="TPUMCR_A" type="CtrlReg" value="0x000"
size="2" accessmode="supervisor">
<description>
TPU3_A Module Configuration Register
</description>
</register>
<register mnemonic="TCR_A" type="CtrlReg" value="0x002" size="2"
accessmode="test">
<description>
TPU3_A Test Configuration Register
</description>
</register>
<register mnemonic="DSCR_A" type="CtrlReg" value="0x004"
size="2" accessmode="supervisor">
<description>
TPU3_A Development Support Control Register
</description>
</register>
<register mnemonic="DSSR_A" type="CtrlReg" value="0x006"
size="2" accessmode="supervisor">
<description>
TPU3_A Development Support Status Register
</description>
</register>
<register mnemonic="TICR_A" type="CtrlReg" value="0x008"
size="2" accessmode="supervisor">
<description>
TPU3_A Interrupt Configuration Register.
</description>
</register>
<register mnemonic="CIER_A" type="CtrlReg" value="0x00a"
size="2" accessmode="supervisor">
<description>
TPU3_A Channel Interrupt Enable Register
</description>
</register>
<register mnemonic="CFSR0_A" type="CtrlReg" value="0x00c"
size="2" accessmode="supervisor">
<description>
TPU3_A Channel Function Selection Register 0.
</description>
</register>
<register mnemonic="CFSR1_A" type="CtrlReg" value="0x00e"
size="2" accessmode="supervisor">
<description>
TPU3_A Channel Function Selection Register 1
</description>
</register>
<register mnemonic="CFSR2_A" type="CtrlReg" value="0x010"
size="2" accessmode="supervisor">
<description>
TPU3_A Channel Function Selection Register 2
</description>
</register>
<register mnemonic="CFSR3_A" type="CtrlReg" value="0x012"
size="2" accessmode="supervisor">
<description>
TPU_A Channel Function Selection Register 3
</description>
</register>
<register mnemonic="HSQR0_A" type="CtrlReg" value="0x014"
size="2">
<description>TPU_A Host Sequence Register 0</description>
</register>
<register mnemonic="HSQR1_A" type="CtrlReg" value="0x016"
size="2">
<description>TPU_A Host Sequence Register 1</description>
</register>
<register mnemonic="HSRR0_A" type="CtrlReg" value="0x018"
size="2">
<description>
TPU_A Host Service Request Register 0
</description>
</register>
<register mnemonic="HSRR1_A" type="CtrlReg" value="0x01a"
size="2">
<description>
TPU_A Host Service Request Register 1
</description>
</register>
<register mnemonic="CPR0_A" type="CtrlReg" value="0x01c"
size="2" accessmode="supervisor">
<description>TPU_A Channel Priority Register 0</description>
</register>
<register mnemonic="CPR1_A" type="CtrlReg" value="0x01e"
size="2" accessmode="supervisor">
<description>TPU_A Channel Priority Register 1</description>
</register>
<register mnemonic="CISR_A" type="CtrlReg" value="0x020"
size="2" accessmode="supervisor">
<description>
TPU_A Channel Interrupt Status Register
</description>
</register>
<register mnemonic="LR_A" type="CtrlReg" value="0x022" size="2"
accessmode="test">
<description>TPU_A Link Register</description>
</register>
<register mnemonic="SGLR_A" type="CtrlReg" value="0x024"
size="2" accessmode="test">
<description>
TPU_A Service Grant Latch Register
</description>
</register>
<register mnemonic="DCNR_A" type="CtrlReg" value="0x026"
size="2" accessmode="test">
<description>
TPU_A Decoded Channel Number Register
</description>
</register>
<register mnemonic="TPUMCR2_A" type="CtrlReg" value="0x028"
size="2" accessmode="supervisor">
<description>
TPU_A Module Configuration Register 2
</description>
</register>
<register mnemonic="TPUMCR3_A" type="CtrlReg" value="0x02a"
size="2" accessmode="supervisor">
<description>
TPU_A Module Configuration Register 3
</description>
</register>
<register mnemonic="ISDR_A" type="CtrlReg" value="0x02c"
size="2" accessmode="test">
<description>TPU_A Internal Scan Data Register</description>
</register>
<register mnemonic="ISCR_A" type="CtrlReg" value="0x02e"
size="2" accessmode="test">
<description>
TPU_A Internal Scan Control Register
</description>
</register>
<!-- TPU_B -->
<register mnemonic="TPUMCR_B" type="CtrlReg" value="0x400"
size="2" accessmode="supervisor">
<description>
TPU3_B Module Configuration Register
</description>
</register>
<register mnemonic="TCR_B" type="CtrlReg" value="0x402" size="2"
accessmode="test">
<description>
TPU3_B Test Configuration Register
</description>
</register>
<register mnemonic="DSCR_B" type="CtrlReg" value="0x404"
size="2" accessmode="supervisor">
<description>
TPU3_B Development Support Control Register
</description>
</register>
<register mnemonic="DSSR_B" type="CtrlReg" value="0x406"
size="2" accessmode="supervisor">
<description>
TPU3_B Development Support Status Register
</description>
</register>
<register mnemonic="TICR_B" type="CtrlReg" value="0x408"
size="2" accessmode="supervisor">
<description>
TPU3_B Interrupt Configuration Register
</description>
</register>
<register mnemonic="CIER_B" type="CtrlReg" value="0x40a"
size="2" accessmode="supervisor">
<description>
TPU3_B Channel Interrupt Enable Register
</description>
</register>
<register mnemonic="CFSR0_B" type="CtrlReg" value="0x40c"
size="2" accessmode="supervisor">
<description>
TPU3_B Channel Function Selection Register 0
</description>
</register>
<register mnemonic="CFSR1_B" type="CtrlReg" value="0x40e"
size="2" accessmode="supervisor">
<description>
TPU3_B Channel Function Selection Register 1
</description>
</register>
<register mnemonic="CFSR2_B" type="CtrlReg" value="0x410"
size="2" accessmode="supervisor">
<description>
TPU3_B Channel Function Selection Register 2
</description>
</register>
<register mnemonic="CFSR3_B" type="CtrlReg" value="0x412"
size="2" accessmode="supervisor">
<description>
TPU_B Channel Function Selection Register 3
</description>
</register>
<register mnemonic="HSQR0_B" type="CtrlReg" value="0x414"
size="2">
<description>TPU_B Host Sequence Register 0</description>
</register>
<register mnemonic="HSQR1_B" type="CtrlReg" value="0x416"
size="2">
<description>TPU_B Host Sequence Register 1</description>
</register>
<register mnemonic="HSRR0_B" type="CtrlReg" value="0x418"
size="2">
<description>
TPU_B Host Service Request Register 0
</description>
</register>
<register mnemonic="HSRR1_B" type="CtrlReg" value="0x41a"
size="2">
<description>
TPU_B Host Service Request Register 1
</description>
</register>
<register mnemonic="CPR0_B" type="CtrlReg" value="0x41c"
size="2" accessmode="supervisor">
<description>TPU_B Channel Priority Register 0</description>
</register>
<register mnemonic="CPR1_B" type="CtrlReg" value="0x41e"
size="2" accessmode="supervisor">
<description>TPU_B Channel Priority Register 1</description>
</register>
<register mnemonic="CISR_B" type="CtrlReg" value="0x420"
size="2" accessmode="supervisor">
<description>
TPU_B Channel Interrupt Status Register
</description>
</register>
<register mnemonic="LR_B" type="CtrlReg" value="0x422" size="2"
accessmode="test">
<description>TPU_B Link Register</description>
</register>
<register mnemonic="SGLR_B" type="CtrlReg" value="0x424"
size="2" accessmode="test">
<description>
TPU_B Service Grant Latch Register
</description>
</register>
<register mnemonic="DCNR_B" type="CtrlReg" value="0x426"
size="2" accessmode="test">
<description>
TPU_B Decoded Channel Number Register
</description>
</register>
<register mnemonic="TPUMCR2_B" type="CtrlReg" value="0x428"
size="2" accessmode="supervisor">
<description>
TPU_B Module Configuration Register 2
</description>
</register>
<register mnemonic="TPUMCR3_B" type="CtrlReg" value="0x42a"
size="2" accessmode="supervisor">
<description>
TPU_B Module Configuration Register 3
</description>
</register>
<register mnemonic="ISDR_B" type="CtrlReg" value="0x42c"
size="2" accessmode="test">
<description>TPU_B Internal Scan Data Register</description>
</register>
<register mnemonic="ISCR_B" type="CtrlReg" value="0x42e"
size="2" accessmode="test">
<description>
TPU_B Internal Scan Control Register
</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x304000">
<!-- QADC64 (Queued Analog-to-Digital Converter) -->
<!-- QADC_A -->
<register mnemonic="QADC64MCR_A" type="CtrlReg" value="0x800"
size="2" accessmode="supervisor">
<description>
QADC64 Module Configuration Register
</description>
</register>
<register mnemonic="QADC64TEST_A" type="CtrlReg" value="0x802"
size="2" accessmode="test">
<description>QADC64 Test Register</description>
</register>
<register mnemonic="QADC64INT_A" type="CtrlReg" value="0x804"
size="2" accessmode="supervisor">
<description>QADC64 Interrupt Register</description>
</register>
<register mnemonic="PORTQA_A" altmnemonic="PORTQB_A"
type="CtrlReg" value="0x806" size="2">
<description>Port A and Port B Data</description>
</register>
<register mnemonic="DDRQA_A" altmnemonic="DDRQB_A"
type="CtrlReg" value="0x808" size="2">
<description>
Port A Data and Port B Direction Register
</description>
</register>
<register mnemonic="QACR0_A" type="CtrlReg" value="0x80a"
size="2">
<description>QADC64 Control Register 0</description>
</register>
<register mnemonic="QACR1_A" type="CtrlReg" value="0x80c"
size="2">
<description>QADC64 Control Register 1</description>
</register>
<register mnemonic="QACR2_A" type="CtrlReg" value="0x80e"
size="2">
<description>QADC64 Control Register 2</description>
</register>
<register mnemonic="QASR0_A" type="CtrlReg" value="0x810"
size="2">
<description>QADC64 Status Register 0</description>
</register>
<register mnemonic="QASR1_A" type="CtrlReg" value="0x812"
size="2">
<description>QADC64 Status Register 1</description>
</register>
<!-- QADC_B -->
<register mnemonic="QADC64MCR_B" type="CtrlReg" value="0xc00"
size="2" accessmode="supervisor">
<description>
QADC64 Module Configuration Register
</description>
</register>
<register mnemonic="QADC64TEST_B" type="CtrlReg" value="0xc02"
size="2" accessmode="test">
<description>QADC64 Test Register</description>
</register>
<register mnemonic="QADC64INT_B" type="CtrlReg" value="0xc04"
size="2" accessmode="supervisor">
<description>QADC64 Interrupt Register</description>
</register>
<register mnemonic="PORTQA_B" altmnemonic="PORTQB_B"
type="CtrlReg" value="0xc06" size="2">
<description>Port A and Port B Data</description>
</register>
<register mnemonic="DDRQA_B" altmnemonic="DDRQB_B"
type="CtrlReg" value="0xc08" size="2">
<description>
Port A Data and Port B Direction Register
</description>
</register>
<register mnemonic="QACR0_B" type="CtrlReg" value="0xc0a"
size="2">
<description>QADC64 Control Register 0</description>
</register>
<register mnemonic="QACR1_B" type="CtrlReg" value="0xc0c"
size="2">
<description>QADC64 Control Register 1</description>
</register>
<register mnemonic="QACR2_B" type="CtrlReg" value="0xc0e"
size="2">
<description>QADC64 Control Register 2</description>
</register>
<register mnemonic="QASR0_B" type="CtrlReg" value="0xc10"
size="2">
<description>QADC64 Status Register 0</description>
</register>
<register mnemonic="QASR1_B" type="CtrlReg" value="0xc12"
size="2">
<description>QADC64 Status Register 1</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x305000">
<!-- QSMCM (Queued Serial Multi-Channel Module) -->
<register mnemonic="QSMCMMCR" type="CtrlReg" value="0x000"
size="2" accessmode="supervisor">
<description>
QSMCM Module Configuration Register
</description>
</register>
<register mnemonic="QTEST" type="CtrlReg" value="0x002" size="2"
accessmode="test">
<description>QSMCM Test Register</description>
</register>
<register mnemonic="QDSCI_IL" type="CtrlReg" value="0x004"
size="2" accessmode="supervisor">
<description>Dual SCI Interrupt Level</description>
</register>
<register mnemonic="QSPI_IL" type="CtrlReg" value="0x006"
size="2" accessmode="supervisor">
<description>Queued SPI Interrupt Level</description>
</register>
<register mnemonic="SCC1R0" type="CtrlReg" value="0x008"
size="2">
<description>SCI1Control Register 0</description>
</register>
<register mnemonic="SCC1R1" type="CtrlReg" value="0x00a"
size="2">
<description>SCI1Control Register 1</description>
</register>
<register mnemonic="SC1SR" type="CtrlReg" value="0x00c"
size="2">
<description>SCI1 Status Register</description>
</register>
<register mnemonic="SC1DR" type="CtrlReg" value="0x00e"
size="2">
<description>SCI1 Data Register</description>
</register>
<register mnemonic="PORTQS" type="CtrlReg" value="0x014"
size="2">
<description>QSMCM Port QS Data Register</description>
</register>
<register mnemonic="PQSPAR" altmnemonic="DDRQST" type="CtrlReg"
value="0x016" size="2">
<description>
QSMCM Port QS PIn Assignment Register / QSMCM Port QS
Data Direction Register
</description>
</register>
<register mnemonic="SPCR0" type="CtrlReg" value="0x018"
size="2">
<description>QSPI Control Register 0</description>
</register>
<register mnemonic="SPCR1" type="CtrlReg" value="0x01a"
size="2">
<description>QSPI Control Register 1</description>
</register>
<register mnemonic="SPCR2" type="CtrlReg" value="0x01c"
size="2">
<description>QSPI Control Register 2</description>
</register>
<register mnemonic="SPCR3" type="CtrlReg" value="0x01e"
size="1">
<description>QSPI Control Register 3</description>
</register>
<register mnemonic="SPSR" type="CtrlReg" value="0x01f"
size="1">
<description>QSPI Status Register 3</description>
</register>
<register mnemonic="SCC2R0" type="CtrlReg" value="0x020"
size="2">
<description>SCI2 Control Register 0</description>
</register>
<register mnemonic="SCC2R1" type="CtrlReg" value="0x022"
size="2">
<description>SCI2 Control Register 1</description>
</register>
<register mnemonic="SC2SR" type="CtrlReg" value="0x024"
size="2">
<description>SCI2 Status Register</description>
</register>
<register mnemonic="SC2DR" type="CtrlReg" value="0x026"
size="2">
<description>SCI2 Data Register</description>
</register>
<register mnemonic="QSCI1CR" type="CtrlReg" value="0x28"
size="2">
<description>QSCI1 Control Register</description>
</register>
<register mnemonic="QSCI1SR" type="CtrlReg" value="0x2a"
size="2">
<description>QSCI1 Status Register</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x306000">
<!-- MIOS1 (Modular Input/Output Subsystem) -->
<!-- MPWMSM0 (MIOS Pulse Width Modulation Submodule 0) -->
<register mnemonic="MPWMSM0PERR" type="CtrlReg" value="0x000"
size="2">
<description>MPWMSM0 Period Register</description>
</register>
<register mnemonic="MPWMSM0PULR" type="CtrlReg" value="0x002"
size="2">
<description>MPWMSM0 Pulse Register</description>
</register>
<register mnemonic="MPWMSM0CNTR" type="CtrlReg" value="0x004"
size="2">
<description>MPWMSM0 Count Register</description>
</register>
<register mnemonic="MPWMSM0SCR" type="CtrlReg" value="0x006"
size="2">
<description>MPWMSM0 Status/Control Register</description>
</register>
<!-- MPWMSM1 (MIOS Pulse Width Modulation Submodule 1) -->
<register mnemonic="MPWMSM1PERR" type="CtrlReg" value="0x008"
size="2">
<description>MPWMSM1 Period Register</description>
</register>
<register mnemonic="MPWMSM1PULR" type="CtrlReg" value="0x00a"
size="2">
<description>MPWMSM1 Pulse Register</description>
</register>
<register mnemonic="MPWMSM1CNTR" type="CtrlReg" value="0x00c"
size="2">
<description>MPWMSM1 Count Register</description>
</register>
<register mnemonic="MPWMSM1SCR" type="CtrlReg" value="0x00e"
size="2">
<description>MPWMSM1 Status/Control Register</description>
</register>
<!-- MPWMSM2 (MIOS Pulse Width Modulation Submodule 2) -->
<register mnemonic="MPWMSM2PERR" type="CtrlReg" value="0x010"
size="2">
<description>MPWMSM2 Period Register</description>
</register>
<register mnemonic="MPWMSM2PULR" type="CtrlReg" value="0x012"
size="2">
<description>MPWMSM2 Pulse Register</description>
</register>
<register mnemonic="MPWMSM2CNTR" type="CtrlReg" value="0x014"
size="2">
<description>MPWMSM2 Count Register</description>
</register>
<register mnemonic="MPWMSM2SCR" type="CtrlReg" value="0x016"
size="2">
<description>MPWMSM2 Status/Control Register</description>
</register>
<!-- MPWMSM3 (MIOS Pulse Width Modulation Submodule 3) -->
<register mnemonic="MPWMSM3PERR" type="CtrlReg" value="0x018"
size="2">
<description>MPWMSM3 Period Register</description>
</register>
<register mnemonic="MPWMSM3PULR" type="CtrlReg" value="0x01a"
size="2">
<description>MPWMSM3 Pulse Register</description>
</register>
<register mnemonic="MPWMSM3CNTR" type="CtrlReg" value="0x01c"
size="2">
<description>MPWMSM3 Count Register</description>
</register>
<register mnemonic="MPWMSM3SCR" type="CtrlReg" value="0x01e"
size="2">
<description>MPWMSM3 Status/Control Register</description>
</register>
<!-- MMCSM6 (MIOS Modulus Counter Submodule 6) -->
<register mnemonic="MMCSM6CNT" type="CtrlReg" value="0x030"
size="2">
<description>MMCSM6 Up-Counter Register</description>
</register>
<register mnemonic="MMCSM6ML" type="CtrlReg" value="0x032"
size="2">
<description>MMCSM6 Modulus Latch Register</description>
</register>
<register mnemonic="MMCSM6SCRD" type="CtrlReg" value="0x034"
size="2">
<description>
MMCSM6 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MMCSM6SCR" type="CtrlReg" value="0x036"
size="2">
<description>MMCSM6 Status/Control Register</description>
</register>
<!-- MDASM11 (MIOS Double Action Submodule 11) -->
<register mnemonic="MDASM11AR" type="CtrlReg" value="0x058"
size="2">
<description>MDASM11 Data A Register</description>
</register>
<register mnemonic="MDASM11BR" type="CtrlReg" value="0x05a"
size="2">
<description>MDASM11 Data B Register</description>
</register>
<register mnemonic="MDASM11SCRD" type="CtrlReg" value="0x05c"
size="2">
<description>
MDASM11 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM11SCR" type="CtrlReg" value="0x05e"
size="2">
<description>MDASM11 Status/Control Register</description>
</register>
<!-- MDASM12 (MIOS Double Action Submodule 12) -->
<register mnemonic="MDASM12AR" type="CtrlReg" value="0x060"
size="2">
<description>MDASM12 Data A Register</description>
</register>
<register mnemonic="MDASM12BR" type="CtrlReg" value="0x062"
size="2">
<description>MDASM12 Data B Register</description>
</register>
<register mnemonic="MDASM12SCRD" type="CtrlReg" value="0x064"
size="2">
<description>
MDASM12 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM12SCR" type="CtrlReg" value="0x066"
size="2">
<description>MDASM12 Status/Control Register</description>
</register>
<!-- MDASM13 (MIOS Double Action Submodule 13) -->
<register mnemonic="MDASM13AR" type="CtrlReg" value="0x068"
size="2">
<description>MDASM13 Data A Register</description>
</register>
<register mnemonic="MDASM13BR" type="CtrlReg" value="0x06a"
size="2">
<description>MDASM13 Data B Register</description>
</register>
<register mnemonic="MDASM13SCRD" type="CtrlReg" value="0x06c"
size="2">
<description>
MDASM13 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM13SCR" type="CtrlReg" value="0x06e"
size="2">
<description>MDASM13 Status/Control Register</description>
</register>
<!-- MDASM14 (MIOS Double Action Submodule 14) -->
<register mnemonic="MDASM14AR" type="CtrlReg" value="0x070"
size="2">
<description>MDASM14 Data A Register</description>
</register>
<register mnemonic="MDASM14BR" type="CtrlReg" value="0x072"
size="2">
<description>MDASM14 Data B Register</description>
</register>
<register mnemonic="MDASM14SCRD" type="CtrlReg" value="0x074"
size="2">
<description>
MDASM14 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM14SCR" type="CtrlReg" value="0x076"
size="2">
<description>MDASM14 Status/Control Register</description>
</register>
<!-- MDASM15 (MIOS Double Action Submodule 15) -->
<register mnemonic="MDASM15AR" type="CtrlReg" value="0x078"
size="2">
<description>MDASM15 Data A Register</description>
</register>
<register mnemonic="MDASM15BR" type="CtrlReg" value="0x07a"
size="2">
<description>MDASM15 Data B Register</description>
</register>
<register mnemonic="MDASM15SCRD" type="CtrlReg" value="0x07c"
size="2">
<description>
MDASM15 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM15SCR" type="CtrlReg" value="0x07e"
size="2">
<description>MDASM15 Status/Control Register</description>
</register>
<!-- MPWMSM16 (MIOS Pulse Width Modulation Submodule 16) -->
<register mnemonic="MPWMSM16PERR" type="CtrlReg" value="0x080"
size="2">
<description>MPWMSM16 Period Register</description>
</register>
<register mnemonic="MPWMSM16PULR" type="CtrlReg" value="0x082"
size="2">
<description>MPWMSM16 Pulse Register</description>
</register>
<register mnemonic="MPWMSM16CNTR" type="CtrlReg" value="0x084"
size="2">
<description>MPWMSM16 Count Register</description>
</register>
<register mnemonic="MPWMSM16SCR" type="CtrlReg" value="0x086"
size="2">
<description>MPWMSM16 Status/Control Register</description>
</register>
<!-- MPWMSM17 (MIOS Pulse Width Modulation Submodule 17) -->
<register mnemonic="MPWMSM17PERR" type="CtrlReg" value="0x088"
size="2">
<description>MPWMSM17 Period Register</description>
</register>
<register mnemonic="MPWMSM17PULR" type="CtrlReg" value="0x08a"
size="2">
<description>MPWMSM17 Pulse Register</description>
</register>
<register mnemonic="MPWMSM17CNTR" type="CtrlReg" value="0x08c"
size="2">
<description>MPWMSM17 Count Register</description>
</register>
<register mnemonic="MPWMSM17SCR" type="CtrlReg" value="0x08e"
size="2">
<description>MPWMSM17 Status/Control Register</description>
</register>
<!-- MPWMSM18 (MIOS Pulse Width Modulation Submodule 18) -->
<register mnemonic="MPWMSM18PERR" type="CtrlReg" value="0x090"
size="2">
<description>MPWMSM18 Period Register</description>
</register>
<register mnemonic="MPWMSM18PULR" type="CtrlReg" value="0x092"
size="2">
<description>MPWMSM18 Pulse Register</description>
</register>
<register mnemonic="MPWMSM18CNTR" type="CtrlReg" value="0x094"
size="2">
<description>MPWMSM18 Count Register</description>
</register>
<register mnemonic="MPWMSM18SCR" type="CtrlReg" value="0x096"
size="2">
<description>MPWMSM18 Status/Control Register</description>
</register>
<!-- MPWMSM19 (MIOS Pulse Width Modulation Submodule 19) -->
<register mnemonic="MPWMSM19PERR" type="CtrlReg" value="0x098"
size="2">
<description>MPWMSM19 Period Register</description>
</register>
<register mnemonic="MPWMSM19PULR" type="CtrlReg" value="0x09a"
size="2">
<description>MPWMSM19 Pulse Register</description>
</register>
<register mnemonic="MPWMSM19CNTR" type="CtrlReg" value="0x09c"
size="2">
<description>MPWMSM19 Count Register</description>
</register>
<register mnemonic="MPWMSM19SCR" type="CtrlReg" value="0x09e"
size="2">
<description>MPWMSM19 Status/Control Register</description>
</register>
<!-- MMCSM22 (MIOS Modulus Counter Submodule 22) -->
<register mnemonic="MMCSM22CNT" type="CtrlReg" value="0x0b0"
size="2">
<description>MMCSM22 Up-Counter Register</description>
</register>
<register mnemonic="MMCSM22ML" type="CtrlReg" value="0x0b2"
size="2">
<description>MMCSM22 Modulus Latch Register</description>
</register>
<register mnemonic="MMCSM22SCRD" type="CtrlReg" value="0x0b4"
size="2">
<description>
MMCSM22 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MMCSM22SCR" type="CtrlReg" value="0x0b6"
size="2">
<description>MMCSM22 Status/Control Register</description>
</register>
<!-- MDASM27 (MIOS Double Action Submodule 27) -->
<register mnemonic="MDASM27AR" type="CtrlReg" value="0x0d8"
size="2">
<description>MDASM27 Data A Register</description>
</register>
<register mnemonic="MDASM27BR" type="CtrlReg" value="0x0da"
size="2">
<description>MDASM27 Data B Register</description>
</register>
<register mnemonic="MDASM27SCRD" type="CtrlReg" value="0x0dc"
size="2">
<description>
MDASM27 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM27SCR" type="CtrlReg" value="0x0de"
size="2">
<description>MDASM27 Status/Control Register</description>
</register>
<!-- MDASM28 (MIOS Double Action Submodule 28) -->
<register mnemonic="MDASM28AR" type="CtrlReg" value="0x0e0"
size="2">
<description>MDASM28 Data A Register</description>
</register>
<register mnemonic="MDASM28BR" type="CtrlReg" value="0x0e2"
size="2">
<description>MDASM28 Data B Register</description>
</register>
<register mnemonic="MDASM28SCRD" type="CtrlReg" value="0x0e4"
size="2">
<description>
MDASM28 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM28SCR" type="CtrlReg" value="0x0e6"
size="2">
<description>MDASM28 Status/Control Register</description>
</register>
<!-- MDASM29 (MIOS Double Action Submodule 29) -->
<register mnemonic="MDASM29AR" type="CtrlReg" value="0x0e8"
size="2">
<description>MDASM29 Data A Register</description>
</register>
<register mnemonic="MDASM29BR" type="CtrlReg" value="0x0ea"
size="2">
<description>MDASM29 Data B Register</description>
</register>
<register mnemonic="MDASM29SCRD" type="CtrlReg" value="0x0ec"
size="2">
<description>
MDASM29 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM29SCR" type="CtrlReg" value="0x0ee"
size="2">
<description>MDASM29 Status/Control Register</description>
</register>
<!-- MDASM30 (MIOS Double Action Submodule 30) -->
<register mnemonic="MDASM30AR" type="CtrlReg" value="0x0f0"
size="2">
<description>MDASM30 Data A Register</description>
</register>
<register mnemonic="MDASM30BR" type="CtrlReg" value="0x0f2"
size="2">
<description>MDASM30 Data B Register</description>
</register>
<register mnemonic="MDASM30SCRD" type="CtrlReg" value="0x0f4"
size="2">
<description>
MDASM30 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM30SCR" type="CtrlReg" value="0x0f6"
size="2">
<description>MDASM30 Status/Control Register</description>
</register>
<!-- MDASM31 (MIOS Double Action Submodule 31) -->
<register mnemonic="MDASM31AR" type="CtrlReg" value="0x0f8"
size="2">
<description>MDASM31 Data A Register</description>
</register>
<register mnemonic="MDASM31BR" type="CtrlReg" value="0x0fa"
size="2">
<description>MDASM31 Data B Register</description>
</register>
<register mnemonic="MDASM31SCRD" type="CtrlReg" value="0x0fc"
size="2">
<description>
MDASM31 Status/Control Register Duplicated
</description>
</register>
<register mnemonic="MDASM31SCR" type="CtrlReg" value="0x0fe"
size="2">
<description>MDASM31 Status/Control Register</description>
</register>
<!-- MPIOSM (MIOS 16-bit Parallel Port I/O Submodule) -->
<register mnemonic="MPIOSMDR" type="CtrlReg" value="0x100"
size="2">
<description>MPIOSM Data Register</description>
</register>
<register mnemonic="MPIOSMDDR" type="CtrlReg" value="0x102"
size="2">
<description>MPIOSM Data Direction Register</description>
</register>
<!-- MBISM (MIOS Bus Interface Submodule) -->
<register mnemonic="MIOS1TPCR" type="CtrlReg" value="0x800"
size="2" accessmode="supervisor">
<description>
MIOS1 Test and Pin Control Register.
</description>
</register>
<register mnemonic="MIOS1VNR" type="CtrlReg" value="0x804"
size="2" accessmode="supervisor" accessattr="readonly">
<description>
MIOS1 Module Version Number Register
</description>
</register>
<register mnemonic="MIOS1MCR" type="CtrlReg" value="0x806"
size="2" accessmode="supervisor">
<description>MIOS1 Module Control Register</description>
</register>
<!-- MCPSM (MIOS Counter Prescaler Submodule) -->
<register mnemonic="MCPSMSCR" type="CtrlReg" value="0x816"
size="2" accessmode="supervisor">
<description>MCPSM Status/Control Register</description>
</register>
<!-- MIRSM0 (MIOS Interrupt Request Submodule 0) -->
<register mnemonic="MIOS1SR0" type="CtrlReg" value="0xc00"
size="2" accessmode="supervisor">
<description>MIRSM0 Interrupt Status Register</description>
</register>
<register mnemonic="MIOS1ER0" type="CtrlReg" value="0xc04"
size="2" accessmode="supervisor">
<description>MIRSM0 Interrupt Enable Register</description>
</register>
<register mnemonic="MIOS1RPR0" type="CtrlReg" value="0xc06"
size="2" accessmode="supervisor" accessattr="readonly">
<description>MIRSM0 Request Pending Register</description>
</register>
<!-- MIRSM (MIOS Interrupt Request Submodule) -->
<register mnemonic="MIOS1LVL0" type="CtrlReg" value="0xc30"
size="2" accessmode="supervisor">
<description>MIOS1 Interrupt Level Register 0</description>
</register>
<!-- MIRSM1 (MIOS Interrupt Request Submodule 1) -->
<register mnemonic="MIOS1SR1" type="CtrlReg" value="0xc40"
size="2" accessmode="supervisor">
<description>MIRSM1 Interrupt Status Register</description>
</register>
<register mnemonic="MIOS1ER1" type="CtrlReg" value="0xc44"
size="2" accessmode="supervisor">
<description>MIRSM1 Interrupt Enable Register</description>
</register>
<register mnemonic="MIOS1RPR1" type="CtrlReg" value="0xc46"
size="2" accessmode="supervisor" accessattr="readonly">
<description>MIRSM1 Request Pending Register</description>
</register>
<!-- MIRSM (MIOS Interrupt Request Submodule) -->
<register mnemonic="MIOS1LVL1" type="CtrlReg" value="0xc70"
size="2" accessmode="supervisor">
<description>MIOS1 Interrupt Level Register 1</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x307000">
<!-- TouCAN (CAN 2.0B Controller) -->
<!-- TouCAN_A -->
<register mnemonic="TCNMCR_A" type="CtrlReg" value="0x080"
size="2" accessmode="supervisor">
<description>
TouCAN_A Module Configuration Register.
</description>
</register>
<register mnemonic="CANTCR_A" type="CtrlReg" value="0x082"
size="2" accessmode="test">
<description>TouCAN_A Test Register</description>
</register>
<register mnemonic="CANICR_A" type="CtrlReg" value="0x084"
size="2" accessmode="supervisor">
<description>
TouCAN_A Interrupt Configuration Register.
</description>
</register>
<register mnemonic="CANCTRL0_A" altmnemonic="CANCTRL1_A"
type="CtrlReg" value="0x086" size="2">
<description>
TouCAN_A Control Register 0 / TouCAN_A Control Register
1
</description>
</register>
<register mnemonic="PRESDIV_A" altmnemonic="CTRL2_A"
type="CtrlReg" value="0x088" size="2">
<description>
TouCAN_A Control and Prescaler Divider Register /
TouCAN_A Control Register 2
</description>
</register>
<register mnemonic="TIMER_A" type="CtrlReg" value="0x08a"
size="2">
<description>
TouCAN_A Free-Running Timer Register.
</description>
</register>
<register mnemonic="RXGMSKHI_A" type="CtrlReg" value="0x090"
size="2">
<description>TouCAN_A Receive Global Mask High</description>
</register>
<register mnemonic="RXGMSKLO_A" type="CtrlReg" value="0x092"
size="2">
<description>TouCAN_A Receive Global Mask Low</description>
</register>
<register mnemonic="RX14MSKHI_A" type="CtrlReg" value="0x094"
size="2">
<description>
TouCAN_A Receive Buffer 14 Mask High
</description>
</register>
<register mnemonic="RX14MSKLO_A" type="CtrlReg" value="0x096"
size="2">
<description>
TouCAN_A Receive Buffer 14 Mask Low
</description>
</register>
<register mnemonic="RX15MSKHI_A" type="CtrlReg" value="0x098"
size="2">
<description>
TouCAN_A Receive Buffer 15 Mask High
</description>
</register>
<register mnemonic="RX15MSKLO_A" type="CtrlReg" value="0x09a"
size="2">
<description>
TouCAN_A Receive Buffer 15 Mask Low
</description>
</register>
<register mnemonic="ESTAT_A" type="CtrlReg" value="0x0a0"
size="2">
<description>
TouCAN_A Error and Status Register
</description>
</register>
<register mnemonic="IMASK_A" type="CtrlReg" value="0x0a2"
size="2">
<description>TouCAN_A Interrupt Masks</description>
</register>
<register mnemonic="IFLAG_A" type="CtrlReg" value="0x0a4"
size="2">
<description>TouCAN_A Interrupt Flags</description>
</register>
<register mnemonic="RXECTR_A" altmnemonic="TXECTR_A"
type="CtrlReg" value="0x0a6" size="2">
<description>
TouCAN_A Receive Error Counter / TouCAN_A Transmit Error
Counter
</description>
</register>
<!-- TouCAN_B -->
<register mnemonic="TCNMCR_B" type="CtrlReg" value="0x480"
size="2" accessmode="supervisor">
<description>
TouCAN_B Module Configuration Register.
</description>
</register>
<register mnemonic="CANTCR_B" type="CtrlReg" value="0x482"
size="2" accessmode="test">
<description>TouCAN_B Test Register</description>
</register>
<register mnemonic="CANICR_B" type="CtrlReg" value="0x484"
size="2" accessmode="supervisor">
<description>
TouCAN_B Interrupt Configuration Register.
</description>
</register>
<register mnemonic="CANCTRL0_B" altmnemonic="CANCTRL1_B"
type="CtrlReg" value="0x486" size="2">
<description>
TouCAN_B Control Register 0 / TouCAN_B Control Register
1
</description>
</register>
<register mnemonic="PRESDIV_B" altmnemonic="CTRL2_B"
type="CtrlReg" value="0x488" size="2">
<description>
TouCAN_B Control and Prescaler Divider Register /
TouCAN_B Control Register 2
</description>
</register>
<register mnemonic="TIMER_B" type="CtrlReg" value="0x48a"
size="2">
<description>
TouCAN_B Free-Running Timer Register.
</description>
</register>
<register mnemonic="RXGMSKHI_B" type="CtrlReg" value="0x490"
size="2">
<description>TouCAN_B Receive Global Mask High</description>
</register>
<register mnemonic="RXGMSKLO_B" type="CtrlReg" value="0x492"
size="2">
<description>TouCAN_B Receive Global Mask Low</description>
</register>
<register mnemonic="RX14MSKHI_B" type="CtrlReg" value="0x494"
size="2">
<description>
TouCAN_B Receive Buffer 14 Mask High
</description>
</register>
<register mnemonic="RX14MSKLO_B" type="CtrlReg" value="0x496"
size="2">
<description>
TouCAN_B Receive Buffer 14 Mask Low
</description>
</register>
<register mnemonic="RX15MSKHI_B" type="CtrlReg" value="0x498"
size="2">
<description>
TouCAN_B Receive Buffer 15 Mask High
</description>
</register>
<register mnemonic="RX15MSKLO_B" type="CtrlReg" value="0x49a"
size="2">
<description>
TouCAN_B Receive Buffer 15 Mask Low
</description>
</register>
<register mnemonic="ESTAT_B" type="CtrlReg" value="0x4a0"
size="2">
<description>
TouCAN_B Error and Status Register
</description>
</register>
<register mnemonic="IMASK_B" type="CtrlReg" value="0x4a2"
size="2">
<description>TouCAN_B Interrupt Masks</description>
</register>
<register mnemonic="IFLAG_B" type="CtrlReg" value="0x4a4"
size="2">
<description>TouCAN_B Interrupt Flags</description>
</register>
<register mnemonic="RXECTR_B" altmnemonic="TXECTR_B"
type="CtrlReg" value="0x4a6" size="2">
<description>
TouCAN_B Receive Error Counter / TouCAN_B Transmit Error
Counter
</description>
</register>
<!-- UIMB (U-Bus to IMB3 Bus Interface) -->
<register mnemonic="UMCR" type="CtrlReg" value="0xf80" size="4"
accessmode="supervisor">
<description>
UIMB Module Configuration Register
</description>
</register>
<register mnemonic="UTSTCREG" type="CtrlReg" value="0xf90"
size="4">
<!-- accessmode should be test + supervisor -->
<description>Test Register — Reserved</description>
</register>
<register mnemonic="UIPEND" type="CtrlReg" value="0xfa0"
size="4" accessmode="supervisor" accessattr="readonly">
<description>Pending Interrupt Request Registe</description>
</register>
</registerGroup>
<registerGroup baseAddress="0x380000">
<!-- SRAM (Static RAM Access Memory) -->
<!-- SRAM_A -->
<register mnemonic="SRAMMCR_A" type="CtrlReg" value="0x000"
size="2" accessmode="supervisor">
<description>
SRAM_A Module Configuration Register
</description>
</register>
<register mnemonic="SRAMTST_A" type="CtrlReg" value="0x004"
size="2" accessmode="test">
<description>SRAM_A Test Register</description>
</register>
<!-- SRAM_A -->
<register mnemonic="SRAMMCR_B" type="CtrlReg" value="0x008"
size="2" accessmode="supervisor">
<description>
SRAM_B Module Configuration Register
</description>
</register>
<register mnemonic="SRAMTST_B" type="CtrlReg" value="0x00c"
size="2" accessmode="test">
<description>SRAM_B Test Register</description>
</register>
</registerGroup>
</registerDefinitions>
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